help with constraint, please

[Brannon King]

I have below a cut from the twr file for a V2. What constraint do I add to
the UCF file such that the rising edge (of my OFDDRTCPEs) is forced to
happen before 7.5 and the falling edge before 15? ISE seems to get it right
without constraints for faster (-6) chips, but I need it to work right for
my slower (-4) chips as well. Thanks for any help.


Clock N180761_CLKPad to Pad
----------------------+------------+------------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
----------------------+------------+------------------------+--------+
N260336_OFDDRTCPE | 10.624(R)|Transport73_pcix_lc_inst| 0.000|
| 16.327(F)|Transport73_pcix_lc_inst| 7.500|
N260337_OFDDRTCPE | 11.003(R)|Transport73_pcix_lc_inst| 0.000|
| 16.638(F)|Transport73_pcix_lc_inst| 7.500|
N260586_OFDDRTCPE | 10.907(R)|Transport73_pcix_lc_inst| 0.000|
| 16.599(F)|Transport73_pcix_lc_inst| 7.500|
N260591_OFDDRTCPE | 11.665(R)|Transport73_pcix_lc_inst| 0.000|
| 16.547(F)|Transport73_pcix_lc_inst| 7.500|


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