Help with clock division question.

K

K8JLF

Guest
I've been messing around with a communications board lately which can have T1
or E1 interfaces. I'd like to change one into the other. Naturally I'll need to
change the framing IC's (and a few other things not related to timing), but I
think for it to run correctly, I need to also change the clock driving them.

Stuff I know:

The T1 framer uses a 1.544mhz master clock
The E1 framer uses a 2.048mhz master clock
The main clock for the whole board is 50.000mhz.
There is only one clock crystal on the board, so everything must be derived
from this crystal I would think.
There are no PLL chips on the board that I can immediately identify
There ARE flip-flops on the board, but I don't see how a flip flop would be
used to generate either of these clock frequencies from a clock of exactly
50.000mhz, since 50.000 does not divide down evenly into either 1.544 or 2.048
There ARE quite a few FPGA's on the board, and the identity of the board
(whether it thinks it's T1 or E1) is determined by the contents of a EEPROM.

My theory right now is that something in firmware looks at what the board
identifies itself as, and decides how to set something in an FPGA that produces
the clocks. Does this seem feasible?

Also, what other methods could it be using to get 1.544mhz and 2.048mhz from
50.000mhz?

The framing IC's in question are Dallas/Maxim DS2152L (T1) and DS2154L (E1). I
have datasheets if anybody wants to have a look.

-C
 
My theory right now is that something in firmware looks at what the board
identifies itself as, and decides how to set something in an FPGA that produces
the clocks. Does this seem feasible?
Click to expand...
One way to run T1/E1 systems is that the "modem" locks on to the
clock from the phone company and uses that for the side that
goes back to the phone company. ("recieve" and "transmit" depend
upon which hat you are wearing.)

Do the receive clock signals from the chips go to a clock-input
pin on the FPGA?

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In article <20041205023315.09736.00000873@mb-m20.aol.com>,
K8JLF <k8jlf@aol.com> wrote:
I've been messing around with a communications board lately which can have T1
or E1 interfaces. I'd like to change one into the other. Naturally I'll need to
change the framing IC's (and a few other things not related to timing), but I
think for it to run correctly, I need to also change the clock driving them.

Stuff I know:

I don't know if this what they did but:
Click to expand...

The T1 framer uses a 1.544mhz master clock
Click to expand...
50MHz / 1.554MHz = 32.3834

If you divide by 32 most of the time but 23 times every 60 cycles you
divide by 33, you get 32.383333. This sort of fractional divider can get
you quite close to the desired frequencies. It is a matter of how many
bits you wish to use up in the extra counters required.

--
--
kensmith@rahul.net forging knowledge
 
I don't know if this what they did but:

The T1 framer uses a 1.544mhz master clock

50MHz / 1.554MHz = 32.3834
Click to expand...
I think you meant 1.544, but I get the idea.

If you divide by 32 most of the time but 23 times every 60 cycles you
divide by 33, you get 32.383333. This sort of fractional divider can get
you quite close to the desired frequencies. It is a matter of how many
bits you wish to use up in the extra counters required.
Click to expand...
Interesting. This doesn't sound like the sort of thing that could be
implemented by cascaded flip-flops though. (since that would only produce an
output of (input clock/some even integer), not something fractional, right?

I can't find any chips on the board that appear to be fancier logic (ie:
counters) that would be doing this. There's some dual flip flops, some octal
flip flops, and a couple of 16-bit edge triggered flip-flops, everything else
is not likely suspects for clock division (FIFO, SRAM, buffers, serial
controllers, etc)

I may have to start taking continuity measurements to see where those signals
are coming from....yuck. The board in question is mostly fine-pitch surface
mount, some of the FGPA's having 240 pins each. Time to buy some needle-tip
probes and set up my luxo magnifier.
 
My theory right now is that something in firmware looks at what the board
identifies itself as, and decides how to set something in an FPGA that
produces
the clocks. Does this seem feasible?

One way to run T1/E1 systems is that the "modem" locks on to the
clock from the phone company and uses that for the side that
goes back to the phone company. ("recieve" and "transmit" depend
upon which hat you are wearing.)
Click to expand...
I've thought of that, but I don't think it's the case because the board I'm
working on would generally be on the phone company end. That and its setting
for transmit clock is "Local Timing". It can also be set to "Loop Timing" which
is what you were referring to. It also supports a method called SRTS, where
data is embedded in ATM cells that gives the difference between source timing
and some network timing reference, and allows timing reconstruction at the far
end. (or at least that's my understanding)

Do the receive clock signals from the chips go to a clock-input
pin on the FPGA?
Click to expand...
I'm going to have to start probing around, I think. I may try making the board
think it's the other one and see if it automatically switches over the timing
to the chips. Might not work, but worth a try.
 
hmurray posted:

(snip)

<< If you look at the right place, you can find the next layer of protocols
where they add/drop a bit occasionally to handle the case where two
phone companies both think they own the one true clock and you want to
use a T1 line between them.
That doesn't sound like any protocol I've seen used. Perhaps you are talking
about a "frame slip" which can happen if one terminal end is experiencing
clock/sync problems.

All central offices synchronize their digital equipment to a source traceable
to a Stratum 1 clock. In practice you will normal never see a frame slip
unless that link is severed and the backup link to a second Stratum 1 clock is
also dead. The days of hierarchical sync between offices is long gone.

Don
 
By the way, what is the frequency of the crystal? I believe I saw an earlier
post that it was 50 MHz. Could it be 50.432 MHz?

Don
 
That doesn't sound like any protocol I've seen used. Perhaps you are talking
about a "frame slip" which can happen if one terminal end is experiencing
clock/sync problems.

All central offices synchronize their digital equipment to a source traceable
to a Stratum 1 clock. In practice you will normal never see a frame slip
unless that link is severed and the backup link to a second Stratum 1 clock
is
also dead. The days of hierarchical sync between offices is long gone.
Click to expand...
Ok, while we're on that subject, what does the stratum 1 clock source generally
consist of? What stratum would timing derived from GPS generally be regarded
as? How about a rubidium clock as found in some cellular base stations? (I have
one of these that I was thinking of trying to set up as a timing source for my
lab.)
 
buried inside them FPGAs no doubt - state machines can eat jobs like this.
Click to expand...
That's the answer I think I'm going to go with for now, and would make sense
since it would allow it to be determined by something in firmware that looks at
what the board is. I'll do another cursory check to see if there's a jumper or
resistor different anywhere, then go with the firmware idea. (The firmware that
loads to the FPGA's as well as the boot ROM is identical between the two
boards, but there is another ROM which contains just the device ID of the board
so it knows what to load as.) Changing that along with the framers and the
resistors related to line impedance may do the trick.
 
It is likely it is inside the FPGA but you could do it in flip-flop
packages if you really wanted to on a 74HC74, both the "D" and "R/" inputs
have to be high when the clock rises to make the "Q" output go high. This
you can make an AND / NAND gate of sorts from the 74HC74. You just need a
lot of chips to get many bits if you want >to go this way.
Click to expand...
Is it even possible to do fractional clock division using flipflops? (not that
I think they really did it in this case) Normally I think of cascaded flip
flops as divide by 2, divide by 2, divide by 2, and on and on. But you can't
get 1.544 or 2.048 this way from 50.000Mhz.
 
k8jlf posted:

<<
That doesn't sound like any protocol I've seen used. Perhaps you are talking
about a "frame slip" which can happen if one terminal end is experiencing
clock/sync problems.

All central offices synchronize their digital equipment to a source traceable
to a Stratum 1 clock. In practice you will normal never see a frame slip
unless that link is severed and the backup link to a second Stratum 1 clock
is
also dead. The days of hierarchical sync between offices is long gone.
Click to expand...
Ok, while we're on that subject, what does the stratum 1 clock source generally
consist of? What stratum would timing derived from GPS generally be regarded
as? How about a rubidium clock as found in some cellular base stations? (I have
one of these that I was thinking of trying to set up as a timing source for my
lab.) >>
--

Stratum 1 is an atomic clock having aq bunch of requirements; I believe the
frequency stability is 1 part in 10E-12.

Many Telco timing systems use GPS as a Stratum 1 traceable source for
synchronizing a local Statum 2 or 3 clock.

Don
 
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