Help with case statement

[Deepu]

Hi All,

I have verilog code with case statements:

3'b000 : begin
casex(reg[10:7])
4'b0xxx : begin $display("ERROR"); end
4'bxx0x : begin $display("ERROR"); end
default : begin $display("NOT POSSIBLE"); end
endcase
end

In this case reg[10:7] will have different values like 1001, 1100, 0100
and so on.

Now if i want to ignore when 4'b0xx0 happens how can this be done.
Because in this particular case, first case will always be displayed.

Please help me on this.

Thanks!

 

[Rajkumar Kadam]

Hi!
In that case just recode it in following way
casex(reg[10:7])
4'b0xx0: begin $display("xxx"); end
default : begin $display ("yyyyyyyy"); end
endcase


Rajkumar...

Deepu wrote:

Hi All,

I have verilog code with case statements:

3'b000 : begin
casex(reg[10:7])
4'b0xxx : begin $display("ERROR"); end
4'bxx0x : begin $display("ERROR"); end
default : begin $display("NOT POSSIBLE"); end
endcase
end

In this case reg[10:7] will have different values like 1001, 1100, 0100
and so on.

Now if i want to ignore when 4'b0xx0 happens how can this be done.
Because in this particular case, first case will always be displayed.

Please help me on this.

Thanks!

 

[John_H]

I usually include my explicit cases rather than trying to ignore one by
order. One way to accomplish your goal would be to have the entry

4'b0xx0 : begin end

The "single statement" of nothing is executed and life goes on. I've
used the empty statement once or twice before but don't typically find a
need for it.


Deepu wrote:

Hi All,

I have verilog code with case statements:

3'b000 : begin
casex(reg[10:7])
4'b0xxx : begin $display("ERROR"); end
4'bxx0x : begin $display("ERROR"); end
default : begin $display("NOT POSSIBLE"); end
endcase
end

In this case reg[10:7] will have different values like 1001, 1100, 0100
and so on.

Now if i want to ignore when 4'b0xx0 happens how can this be done.
Because in this particular case, first case will always be displayed.

Please help me on this.

Thanks!