T
Tony Benham
Guest
I have a problem with a xilinx virtex2 design, and specifying the timing
constraints for a pair of clocks in the design.
Most of the design is clocked by either a x1 clk, or a div2 clk (which is
hence half the frequency). Both the x1 and div2 clock are generated in a
dcm, locked to a x1 input clock. I select which clock to use via a global
clock mux BUFGMUX. I have placed a TS on the ouptut clock of the BUFGMUX,
which is x1 so that I can be sure the circuitry driven by this clock will
run at the faster x1 clock rate. I also put timing constraints on the two
clocks out of the dcm, and the input clock pin. The Post PAR timing analyser
tells me that there are no timing errors.
The design is fine most of the time, but occasionally I get problems where
part of the design stops working correctly, but is fixed by a new par.
I investigated the timing more carefully, and used the constraints
interaction report from the timing analyzer to see what might be going on.
What I find in that report is that my timing constraint on the BUFGMUX
output clock is shown to be overridden by the div2 clock specification,
which is half the frequency. This may explain why I'm having problems.
Nearly 2 months ago I contacted european xilinx support, but the guy dealing
with my case says he isn't an expert on timing, and keeps coming back
(supposedly after discussion with a more expert engineer) with ideas to try,
such as putting TIG on the clocks etc. None of these have worked. I'm not
totally sure the guy understands my problem.
Does anyone have experience with this type of problem, or have any ideas how
I can escalate the problem with Xilinx, and speak to a more knowledgeable
engineer ?
Regards
Tony Benham
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constraints for a pair of clocks in the design.
Most of the design is clocked by either a x1 clk, or a div2 clk (which is
hence half the frequency). Both the x1 and div2 clock are generated in a
dcm, locked to a x1 input clock. I select which clock to use via a global
clock mux BUFGMUX. I have placed a TS on the ouptut clock of the BUFGMUX,
which is x1 so that I can be sure the circuitry driven by this clock will
run at the faster x1 clock rate. I also put timing constraints on the two
clocks out of the dcm, and the input clock pin. The Post PAR timing analyser
tells me that there are no timing errors.
The design is fine most of the time, but occasionally I get problems where
part of the design stops working correctly, but is fixed by a new par.
I investigated the timing more carefully, and used the constraints
interaction report from the timing analyzer to see what might be going on.
What I find in that report is that my timing constraint on the BUFGMUX
output clock is shown to be overridden by the div2 clock specification,
which is half the frequency. This may explain why I'm having problems.
Nearly 2 months ago I contacted european xilinx support, but the guy dealing
with my case says he isn't an expert on timing, and keeps coming back
(supposedly after discussion with a more expert engineer) with ideas to try,
such as putting TIG on the clocks etc. None of these have worked. I'm not
totally sure the guy understands my problem.
Does anyone have experience with this type of problem, or have any ideas how
I can escalate the problem with Xilinx, and speak to a more knowledgeable
engineer ?
Regards
Tony Benham
---
Outgoing mail is certified Virus Free.
Checked by AVG anti-virus system (http://www.grisoft.com).
Version: 6.0.576 / Virus Database: 365 - Release Date: 30/01/2004
