Help with Assinc counter

[Sink0]

Hi, i need to use an package counter to check how many packages are
inside a dual port FIFO. The counter should increment the counter at
the posedge of one port and decrement with posedge of another port,
and a third port would stay at log state high if there are full
packages inside the FIFO. I think the idea would be the same of the
implementation of the Async FIFO, but i could not understand how the
process works reading the article "Simulation and Synthesis Techniques
for Asynchronous FIFO Design". Any one could give me a simple
explanation on how implement that counter on Verilog?

Thank you!

 

[RCIngham]

Hi, i need to use an package counter to check how many packages are
inside a dual port FIFO. The counter should increment the counter at
the posedge of one port and decrement with posedge of another port,
and a third port would stay at log state high if there are full
packages inside the FIFO. I think the idea would be the same of the
implementation of the Async FIFO, but i could not understand how the
process works reading the article "Simulation and Synthesis Techniques
for Asynchronous FIFO Design". Any one could give me a simple
explanation on how implement that counter on Verilog?

Thank you!

The counter has to be in one clock domain or the other. I will assume tha
it will be in the first clock domain.

Use the posedge of the first port to generate a 'count-up' strobe.
Use the posedge of the second port, via a clock-domain-crossing puls
synchronizer, to generate a 'count_down' strobe.
I don't quite understand what the third port is doing. Is it a "count no
zero" indicator?
The up/down counter should now be easy to code, using only one clock.

The design of pulse synchronizer can be found in another of Cliff Cummings
excellent papers on the Sunburst website.

I design in VHDL, so cannnot help you with Verilog codes.


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[Sink0]

On Apr 20, 5:33 am, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

Hi, i need to use an package counter to check how many packages are
inside a dual port FIFO. The counter should increment the counter at
the posedge of one port and decrement with posedge of another port,
and a third port would stay at log state high if there are full
packages inside the FIFO. I think the idea would be the same of the
implementation of the Async FIFO, but i could not understand how the
process works reading the article "Simulation and Synthesis Techniques
for Asynchronous FIFO Design". Any one could give me a simple
explanation on how implement that counter on Verilog?

Thank you!

The counter has to be in one clock domain or the other. I will assume that
it will be in the first clock domain.

Use the posedge of the first port to generate a 'count-up' strobe.
Use the posedge of the second port, via a clock-domain-crossing pulse
synchronizer, to generate a 'count_down' strobe.
I don't quite understand what the third port is doing. Is it a "count not
zero" indicator?
The up/down counter should now be easy to code, using only one clock.

The design of pulse synchronizer can be found in another of Cliff Cummings'
excellent papers on the Sunburst website.

I design in VHDL, so cannnot help you with Verilog codes.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

I dont know if it is possible, but the idea is to not have a clock
domain. It is a counter with 3 ports. 2 inputs and one output. at
every pulse at input 1 the counter goes up, at every pulse at the
input 2 the counter goes down. If the counter is on 0 the output is
0, if the counter value is bigger than 0 the output is 1. But the
pulses will be assinc generated. I will have a fifo, and i got to
control how many full messages packages are inside, but the packages
len is variable, so there is a module that parse the message at the
input to pulse when a full message is inside and another to parse the
output to check when a full message came out, to generae a pulse to
the counter. Is that possible?

Thank you!

 

[RCIngham]

I dont know if it is possible, but the idea is to not have a clock
domain.

FPGAs are intended for the implementation of synchronous logic, with
limited number of different clock domains.


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