Help with Address load logic

[Syed Huq]

Hi,

I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a trigger. I have an address generator which is basically a counter and when the trigger occurs, it starts to count up and lasts only for the duration of the number of samples. The address is then stored in the register.

Now when the next trigger occurs, I'm trying to load back the stored register address but I'm not certain what to use as the load signal for the counter, since I'm using the trigger signal itself as the enable. Does anyone have any suggestions for the logic ?

Thanks!

 

[Syed Huq]

One BRAM is storing all the data samples from the ADC and since I also need the pre-trigger data samples due to the delay, I'm then transferring over the samples including some pre-trigger data to the second BRAM. The system can have any number of triggers and I'm using the second BRAM to store all the data from the triggers. I just need the data from the trigger events and not all the data being captured.

So my first BRAM is a simple dual-port RAM while my second BRAM is just a simple single-port RAM. My idea is that when the trigger event occurs, I capture the address of the first BRAM at which the trigger occurs, set an offset for the pre-trigger data and use the second address bus to read data from the first BRAM and start writing only the trigger data to the second BRAM.. There may be multiple triggers, but I'll be only storing the trigger data in the second BRAM which is what I need.

On Monday, 14 July 2014 13:36:14 UTC-5, Gabor wrote:

Syed Huq wrote:

Hi,



I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a trigger. I have an address generator which is basically a counter and when the trigger occurs, it starts to count up and lasts only for the duration of the number of samples. The address is then stored in the register.



Now when the next trigger occurs, I'm trying to load back the stored register address but I'm not certain what to use as the load signal for the counter, since I'm using the trigger signal itself as the enable. Does anyone have any suggestions for the logic ?



Thanks!



I'd suggest re-thinking the system. Copying data from one BRAM to

another is an inefficient use of hardware. Why are you doing it?

Is the idea just to have data from the two most recent triggers?

If so, then why not just alternate capture between the two BRAM's

and just keep track of which one was used last.



--

Gabor

 

[GaborSzakacs]

Syed Huq wrote:

Hi,

I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a trigger. I have an address generator which is basically a counter and when the trigger occurs, it starts to count up and lasts only for the duration of the number of samples. The address is then stored in the register.

Now when the next trigger occurs, I'm trying to load back the stored register address but I'm not certain what to use as the load signal for the counter, since I'm using the trigger signal itself as the enable. Does anyone have any suggestions for the logic ?

Thanks!

I'd suggest re-thinking the system. Copying data from one BRAM to
another is an inefficient use of hardware. Why are you doing it?
Is the idea just to have data from the two most recent triggers?
If so, then why not just alternate capture between the two BRAM's
and just keep track of which one was used last.

--
Gabor

 

[Andy Bartlett]

"Syed Huq" <syed.huq.a@gmail.com> wrote in message
news:751fcc59-d1ac-4195-8b17-b5618dfb2f20@googlegroups.com...
Hi,

I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the
data samples from the ADC and another BRAM just transferring samples from
the 1st BRAM to the 2nd on the event of a trigger. I have an address
generator which is basically a counter and when the trigger occurs, it
starts to count up and lasts only for the duration of the number of samples.
The address is then stored in the register.

Now when the next trigger occurs, I'm trying to load back the stored
register address but I'm not certain what to use as the load signal for the
counter, since I'm using the trigger signal itself as the enable. Does
anyone have any suggestions for the logic ?

Thanks!



Why not just swop the BRAM's over ping pong style on the next trigger? Or
use one BRAM as a dual port with the address MSb on the Write port, and !MSb
on the Read port, and use an XOR to invert the input MSb ( and consequently
!MSb ) from trigger to trigger.

Andy

 

[glen herrmannsfeldt]

Syed Huq <syed.huq.a@gmail.com> wrote:

I'm trying to implement a trigger with 2 BRAMs with one BRAM
storing all the data samples from the ADC and another BRAM just
transferring samples from the 1st BRAM to the 2nd on the event
of a trigger.

I presume you want some about of data before and after the trigger.

In that case, I would store data as a circular buffer, with the
address wrapping when it go to the end. Then when a trigger comes
in, count the appropriat number of additional cycles, still
storing them in the same RAM. From the address at either the
trigger or at the end, you can figure out where the samples are
from before and after.

If you have enough RAMs, or divide up the address space appropriately,
you can use many such circular buffers.

The only complication, and it will be easy to figure out with
software at the end, is the case where two triggers come close
enough together that it hasn't finished one before it needs
to start the next. Just fix that up in software after you
read the data out.

Each circular buffer needs to be long enough to hold the samples
before and after the trigger, no more.

I have an address generator which is basically a counter and
when the trigger occurs, it starts to count up and lasts only
for the duration of the number of samples. The address is then
stored in the register.

-- glen

 

[rickman]

On 7/14/2014 3:30 PM, Syed Huq wrote:

One BRAM is storing all the data samples from the ADC and since I also need the pre-trigger data samples due to the delay, I'm then transferring over the samples including some pre-trigger data to the second BRAM. The system can have any number of triggers and I'm using the second BRAM to store all the data from the triggers. I just need the data from the trigger events and not all the data being captured.

So my first BRAM is a simple dual-port RAM while my second BRAM is just a simple single-port RAM. My idea is that when the trigger event occurs, I capture the address of the first BRAM at which the trigger occurs, set an offset for the pre-trigger data and use the second address bus to read data from the first BRAM and start writing only the trigger data to the second BRAM. There may be multiple triggers, but I'll be only storing the trigger data in the second BRAM which is what I need.

On Monday, 14 July 2014 13:36:14 UTC-5, Gabor wrote:
Syed Huq wrote:

Hi,



I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a trigger. I have an address generator which is basically a counter and when the trigger occurs, it starts to count up and lasts only for the duration of the number of samples. The address is then stored in the register.



Now when the next trigger occurs, I'm trying to load back the stored register address but I'm not certain what to use as the load signal for the counter, since I'm using the trigger signal itself as the enable. Does anyone have any suggestions for the logic ?



Thanks!



I'd suggest re-thinking the system. Copying data from one BRAM to

another is an inefficient use of hardware. Why are you doing it?

Is the idea just to have data from the two most recent triggers?

If so, then why not just alternate capture between the two BRAM's

and just keep track of which one was used last.
--

Gabor

I'm with Gabor. I think I understand what you are doing and I would say
you can do it better without the second BRAM. You are using the entire
first BRAM as a circular buffer to capture the data around the trigger.
Then you copy just that data around the trigger to the second BRAM for
multiple triggers, appending the data each time.

This does not require two BRAMs. If you can't think of how to time the
operations and generate the addresses, that shows it is a bit overly
complex.

I would logically divide one BRAM into multiple circular buffers. The
first trigger just stores data in the small region allocated for it (the
same size as the data you wish to see). The second capture uses the
second region of the one BRAM and so on. The only complication of this
method is that each trigger must save the starting address for the data
in the corresponding circular buffer. That could be in the same buffer
memory or in a separate buffer. The software that reads out the memory
can unwrap the circular buffer as it reads out the data by knowing the
starting address of the data and the bounds of the circular buffer.

I honestly can't give you a suggestion about your original question
because I don't understand what you are describing with the addresses
and registers. You can certainly make the two BRAMs do what you want.
If you want to do it that way, I just need to understand better what you
are describing.

You have a trigger circuit that is filling the first BRAM as a circular
buffer. When armed it increments an address register continuously. On
the trigger a length counter is started (I would use a down counter)
that counts the number of samples to store following the trigger. When
that counter expires the address register is loaded with the current
address minus the size of the data you wish to transfer. The length
counter is also reloaded with the number of samples you wish to transfer
and transfers begin to the second BRAM. When the length counter expires
a second time the transfers stop. At this point you can either rearm
the trigger or stop everything and wait for a trigger arming signal.

--

Rick

 

[Syed Huq]

I'm not sure I explained clearly what is going on.

About BRAM1 :

- It's a simple-dual port RAM with two address busses, one to write data to it and the other to read data from it.
- It stores all data samples from the ADC irrespective of the trigger.

BRAM2 :

- It is a single port RAM where the D_OUT of BRAM1 is connected to the D_IN of the BRAM2

The trigger is basically a register value which goes high. When the value goes high, I'm capturing the address of the first address bus of the BRAM1. I'm offsetting that address to accomodate the pre-trigger data, and then use this address value to read data from the BRAM1 and write it to the BRAM2.

I'm generating the addresses using up counters. For the address 1 of the BRAM1, it is a simple up-counter which just keeps counting up. Now for the second address value of the BRAM1, it would be the = (first value - offset) and then load this value into the counter and count up for a certain number of samples. Simultaneously, I count up the up-counter for the address of the BRAM2 and store these trigger samples in BRAM2 until the trigger event is done.

Once the trigger event is done, I stop reading from BRAM1 and also stop the address counter for BRAM2. Now the up counter has a load and enable signal.. The enable signal is used for counting up while the load signal is used to load the start address. For the address counter of the second BRAM, I'm using the trigger event as the enable, but I'm not able to figure out how to load the address value of the last trigger sample from the previous trigger so that I can store the next trigger data, right after the first trigger data ends. I'm not sure what to use as the load signal.

I hope I made more sense this time.

On Monday, 14 July 2014 23:51:47 UTC-5, rickman wrote:

On 7/14/2014 3:30 PM, Syed Huq wrote:

One BRAM is storing all the data samples from the ADC and since I also need the pre-trigger data samples due to the delay, I'm then transferring over the samples including some pre-trigger data to the second BRAM. The system can have any number of triggers and I'm using the second BRAM to store all the data from the triggers. I just need the data from the trigger events and not all the data being captured.



So my first BRAM is a simple dual-port RAM while my second BRAM is just a simple single-port RAM. My idea is that when the trigger event occurs, I capture the address of the first BRAM at which the trigger occurs, set an offset for the pre-trigger data and use the second address bus to read data from the first BRAM and start writing only the trigger data to the second BRAM. There may be multiple triggers, but I'll be only storing the trigger data in the second BRAM which is what I need.



On Monday, 14 July 2014 13:36:14 UTC-5, Gabor wrote:

Syed Huq wrote:



Hi,







I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a trigger. I have an address generator which is basically a counter and when the trigger occurs, it starts to count up and lasts only for the duration of the number of samples. The address is then stored in the register.







Now when the next trigger occurs, I'm trying to load back the stored register address but I'm not certain what to use as the load signal for the counter, since I'm using the trigger signal itself as the enable. Does anyone have any suggestions for the logic ?







Thanks!







I'd suggest re-thinking the system. Copying data from one BRAM to



another is an inefficient use of hardware. Why are you doing it?



Is the idea just to have data from the two most recent triggers?



If so, then why not just alternate capture between the two BRAM's



and just keep track of which one was used last.

--



Gabor



I'm with Gabor. I think I understand what you are doing and I would say

you can do it better without the second BRAM. You are using the entire

first BRAM as a circular buffer to capture the data around the trigger.

Then you copy just that data around the trigger to the second BRAM for

multiple triggers, appending the data each time.



This does not require two BRAMs. If you can't think of how to time the

operations and generate the addresses, that shows it is a bit overly

complex.



I would logically divide one BRAM into multiple circular buffers. The

first trigger just stores data in the small region allocated for it (the

same size as the data you wish to see). The second capture uses the

second region of the one BRAM and so on. The only complication of this

method is that each trigger must save the starting address for the data

in the corresponding circular buffer. That could be in the same buffer

memory or in a separate buffer. The software that reads out the memory

can unwrap the circular buffer as it reads out the data by knowing the

starting address of the data and the bounds of the circular buffer.



I honestly can't give you a suggestion about your original question

because I don't understand what you are describing with the addresses

and registers. You can certainly make the two BRAMs do what you want.

If you want to do it that way, I just need to understand better what you

are describing.



You have a trigger circuit that is filling the first BRAM as a circular

buffer. When armed it increments an address register continuously. On

the trigger a length counter is started (I would use a down counter)

that counts the number of samples to store following the trigger. When

that counter expires the address register is loaded with the current

address minus the size of the data you wish to transfer. The length

counter is also reloaded with the number of samples you wish to transfer

and transfers begin to the second BRAM. When the length counter expires

a second time the transfers stop. At this point you can either rearm

the trigger or stop everything and wait for a trigger arming signal.



--



Rick

 

[rickman]

On 7/15/2014 10:36 PM, Syed Huq wrote:

I'm not sure I explained clearly what is going on.

About BRAM1 :

- It's a simple-dual port RAM with two address busses, one to write data to it and the other to read data from it.
- It stores all data samples from the ADC irrespective of the trigger.

BRAM2 :

- It is a single port RAM where the D_OUT of BRAM1 is connected to the D_IN of the BRAM2

The trigger is basically a register value which goes high. When the value goes high, I'm capturing the address of the first address bus of the BRAM1. I'm offsetting that address to accomodate the pre-trigger data, and then use this address value to read data from the BRAM1 and write it to the BRAM2.

I'm generating the addresses using up counters. For the address 1 of the BRAM1, it is a simple up-counter which just keeps counting up. Now for the second address value of the BRAM1, it would be the = (first value - offset) and then load this value into the counter and count up for a certain number of samples. Simultaneously, I count up the up-counter for the address of the BRAM2 and store these trigger samples in BRAM2 until the trigger event is done.

Once the trigger event is done, I stop reading from BRAM1 and also stop the address counter for BRAM2. Now the up counter has a load and enable signal.. The enable signal is used for counting up while the load signal is used to load the start address. For the address counter of the second BRAM, I'm using the trigger event as the enable, but I'm not able to figure out how to load the address value of the last trigger sample from the previous trigger so that I can store the next trigger data, right after the first trigger data ends. I'm not sure what to use as the load signal.

I hope I made more sense this time.

On Monday, 14 July 2014 23:51:47 UTC-5, rickman wrote:
On 7/14/2014 3:30 PM, Syed Huq wrote:

One BRAM is storing all the data samples from the ADC and since I also need the pre-trigger data samples due to the delay, I'm then transferring over the samples including some pre-trigger data to the second BRAM. The system can have any number of triggers and I'm using the second BRAM to store all the data from the triggers. I just need the data from the trigger events and not all the data being captured.



So my first BRAM is a simple dual-port RAM while my second BRAM is just a simple single-port RAM. My idea is that when the trigger event occurs, I capture the address of the first BRAM at which the trigger occurs, set an offset for the pre-trigger data and use the second address bus to read data from the first BRAM and start writing only the trigger data to the second BRAM. There may be multiple triggers, but I'll be only storing the trigger data in the second BRAM which is what I need.



On Monday, 14 July 2014 13:36:14 UTC-5, Gabor wrote:

Syed Huq wrote:



Hi,







I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all the data samples from the ADC and another BRAM just transferring samples from the 1st BRAM to the 2nd on the event of a trigger. I have an address generator which is basically a counter and when the trigger occurs, it starts to count up and lasts only for the duration of the number of samples. The address is then stored in the register.







Now when the next trigger occurs, I'm trying to load back the stored register address but I'm not certain what to use as the load signal for the counter, since I'm using the trigger signal itself as the enable. Does anyone have any suggestions for the logic ?







Thanks!







I'd suggest re-thinking the system. Copying data from one BRAM to



another is an inefficient use of hardware. Why are you doing it?



Is the idea just to have data from the two most recent triggers?



If so, then why not just alternate capture between the two BRAM's



and just keep track of which one was used last.

--



Gabor



I'm with Gabor. I think I understand what you are doing and I would say

you can do it better without the second BRAM. You are using the entire

first BRAM as a circular buffer to capture the data around the trigger.

Then you copy just that data around the trigger to the second BRAM for

multiple triggers, appending the data each time.



This does not require two BRAMs. If you can't think of how to time the

operations and generate the addresses, that shows it is a bit overly

complex.



I would logically divide one BRAM into multiple circular buffers. The

first trigger just stores data in the small region allocated for it (the

same size as the data you wish to see). The second capture uses the

second region of the one BRAM and so on. The only complication of this

method is that each trigger must save the starting address for the data

in the corresponding circular buffer. That could be in the same buffer

memory or in a separate buffer. The software that reads out the memory

can unwrap the circular buffer as it reads out the data by knowing the

starting address of the data and the bounds of the circular buffer.



I honestly can't give you a suggestion about your original question

because I don't understand what you are describing with the addresses

and registers. You can certainly make the two BRAMs do what you want.

If you want to do it that way, I just need to understand better what you

are describing.



You have a trigger circuit that is filling the first BRAM as a circular

buffer. When armed it increments an address register continuously. On

the trigger a length counter is started (I would use a down counter)

that counts the number of samples to store following the trigger. When

that counter expires the address register is loaded with the current

address minus the size of the data you wish to transfer. The length

counter is also reloaded with the number of samples you wish to transfer

and transfers begin to the second BRAM. When the length counter expires

a second time the transfers stop. At this point you can either rearm

the trigger or stop everything and wait for a trigger arming signal.

I understand what you are doing. You are capturing a small set of
samples around a trigger point. My point is that you don't need to use
the entire BRAM1 to store what I believe is a smaller set of data you
are interested in.

How many samples do you transfer to BRAM2? That is as large as you need
to make your circular buffer.

My point is that you can divide BRAM1 into logical buffers and capture
the data into each one without copying anything to a second BRAM. Is
that not clear? All you need to do is when the trigger happens, count
the additional samples you wish recorded in the circular buffer and
stop, then you are done recording and all the data you want is in the
buffer. No need to copy it out until it is ready for display. Don't
think that a circular buffer has to be as large as the physical BRAM.

As to your question, that is a very small detail that depends on the
details of your logic. I'm not sure you even need to load an address
since the sample blocks can be adjacent in BRAM2. So you can use a
single up counter to address BRAM2, incrementing it on every sample
stored. It reaches N after moving N samples. So block 2 in BRAM2 will
start at location N with the 1st sample in the second block.

--

Rick