Help: Why synthesis tool can not synthesis this logic???

[chip algernon]

Can someone tell me why some synthesis tool (synopsys, simplicity) can
not correctly pass the parameter in case <A>, <B> and <C> to
sub_module?

synopsys can only pass parameter in case <B>, but failed in <A> and
<C>

simplicity failed on <C>.

thanks in advance!

Chip


// ---------------------- example starts here -------------------//


module my_sub_module (in, clk, rstbar, out);

parameter SIZER = 1;
parameter INIT = {32{1'b0}};

input clk, rstbar;
input [SIZER-1:0] in;
output [SIZER-1:0] out;

reg [SIZER-1:0] out;

always @(posedge clk or negedge rstbar)
if (~rstbar)
out <= INIT[SIZER-1:0];
else
out <= in;
endmodule


// ---------------------------------------------------------------------


module top (clk, rstbar, in1, out1, out2, out3);

input clk, rstbar;
input [3:0] in1;
output [3:0] out1, out2, out3;

parameter PASS_PARAM = 32'hFFFF_FFFF;

//<A>
my_sub_module #(4, PASS_PARAM) my_sub_module_0
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out1));

//<B>
my_sub_module #(4, 4294967295) my_sub_module_1
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out2));

//<C>
my_sub_module #(4, PASS_PARAM[3:0]) my_sub_module_2
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out3));

endmodule // top

 

[fabbl]

Chip,

Try posting this on comp.arch.fpga and comp.lang.vhdl also.

fabbl

"chip algernon" <whyalgernon@hotmail.com> wrote in message
news:87c9d883.0403091501.191df137@posting.google.com...

Can someone tell me why some synthesis tool (synopsys, simplicity) can
not correctly pass the parameter in case <A>, <B> and <C> to
sub_module?

synopsys can only pass parameter in case <B>, but failed in <A> and
C

simplicity failed on <C>.

thanks in advance!

Chip


// ---------------------- example starts here -------------------//


module my_sub_module (in, clk, rstbar, out);

parameter SIZER = 1;
parameter INIT = {32{1'b0}};

input clk, rstbar;
input [SIZER-1:0] in;
output [SIZER-1:0] out;

reg [SIZER-1:0] out;

always @(posedge clk or negedge rstbar)
if (~rstbar)
out <= INIT[SIZER-1:0];
else
out <= in;
endmodule


// ---------------------------------------------------------------------


module top (clk, rstbar, in1, out1, out2, out3);

input clk, rstbar;
input [3:0] in1;
output [3:0] out1, out2, out3;

parameter PASS_PARAM = 32'hFFFF_FFFF;

//<A
my_sub_module #(4, PASS_PARAM) my_sub_module_0
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out1));

//<B
my_sub_module #(4, 4294967295) my_sub_module_1
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out2));

//<C
my_sub_module #(4, PASS_PARAM[3:0]) my_sub_module_2
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out3));

endmodule // top

 

[Amit Gupta]

Hi,

The paramater value you are using is outside the scope of a signed 32
bit integer. What you need to confirm from Verilog-LRM (and what I think
is happening here..) .. paramter values are read in a signed-32 bit
integer by the compiler and you are having an over-flow in that value read.

In your case, reading a value 0xffffffff using a signed-32bit integer
will result in an overflow and different compiler will probably behave
with unpredicatble results.

--Amit

chip algernon wrote:

Can someone tell me why some synthesis tool (synopsys, simplicity) can
not correctly pass the parameter in case <A>, <B> and <C> to
sub_module?

synopsys can only pass parameter in case <B>, but failed in <A> and
C

simplicity failed on <C>.

thanks in advance!

Chip


// ---------------------- example starts here -------------------//


module my_sub_module (in, clk, rstbar, out);

parameter SIZER = 1;
parameter INIT = {32{1'b0}};

input clk, rstbar;
input [SIZER-1:0] in;
output [SIZER-1:0] out;

reg [SIZER-1:0] out;

always @(posedge clk or negedge rstbar)
if (~rstbar)
out <= INIT[SIZER-1:0];
else
out <= in;
endmodule


// ---------------------------------------------------------------------


module top (clk, rstbar, in1, out1, out2, out3);

input clk, rstbar;
input [3:0] in1;
output [3:0] out1, out2, out3;

parameter PASS_PARAM = 32'hFFFF_FFFF;

//<A
my_sub_module #(4, PASS_PARAM) my_sub_module_0
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out1));

//<B
my_sub_module #(4, 4294967295) my_sub_module_1
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out2));

//<C
my_sub_module #(4, PASS_PARAM[3:0]) my_sub_module_2
(.in(in1), .clk(clk), .rstbar(rstbar), .out(out3));

endmodule // top