J
Jam
Guest
I don't get it:
I use the libraries:
Library IEEE;
Use IEEE.Std_logic_1164.all;
Use IEEE.Std_logic_unsigned.all;
I have a one compl ADC
temp(11 downto 0) <= (not FOCADCd(11) & FOCADCd(10 downto 0));
SAin(11 downto 0) <= SHL(temp,"10");
should this do the same as SAin(11 downto 0) <= SAin(11 downto 0) <=
(Temp(10 downto 0) & '0');
I use the libraries:
Library IEEE;
Use IEEE.Std_logic_1164.all;
Use IEEE.Std_logic_unsigned.all;
I have a one compl ADC
temp(11 downto 0) <= (not FOCADCd(11) & FOCADCd(10 downto 0));
SAin(11 downto 0) <= SHL(temp,"10");
should this do the same as SAin(11 downto 0) <= SAin(11 downto 0) <=
(Temp(10 downto 0) & '0');