Mar 23, 2006 #1 A absr Guest Hi Can anybody tell me How to interface VHDL generic port map with verilog model? Thanks in advance
Mar 23, 2006 #2 M Mike Treseler Guest absr wrote: Can anybody tell me How to interface VHDL generic port map with verilog model? Click to expand... http://groups.google.com/groups?q=modelsim+mixed+verilog+vhdl+port+map
absr wrote: Can anybody tell me How to interface VHDL generic port map with verilog model? Click to expand... http://groups.google.com/groups?q=modelsim+mixed+verilog+vhdl+port+map
