Help! Verilog compile error on modelSim

[thomasc]

Hi,
I'm stuck in a situation that I don't understand and need some help.

From a Verilog module, called 'abc.v', I instantiated another module,
'def.v'.
While compiling 'abc.v' using ModelSim 5.8c, I got an error message as
follows:

# ** Error: C:/ ..... abc.v(28): Undefined variable: def

I don't understand it because 'b.v' module is in the same project with
'abc.v' and it has passed its own testbench. and it seems that 'a.v' does
not 'know' that 'def.v' is another module. Below is abc.v file.

==================================

module abc (Sx_val, Sx_exp, Sa, Sb);

output [7:0] Sx_val, Sx_exp;
input [7:0] Sa, Sb;

wire [7:0] Sa, Sb;
reg [7:0] Sa_temp, Sb_temp;
reg [7:0] alpha_table;


always @ (Sa or Sb) begin
if (Sa==0) begin
Sx_val = 8'h00;
Sx_exp = 8'h10;
end //if

else begin
if (Sb==0) begin
Sx_val = 8'h00;
Sx_exp = 8'h10;
end
end //else

def E1 (.exp_val(Sa_temp), .index(Sa));
def E2 (.exp_val(Sb_temp), .index(Sb));
Sa_temp = Sa_temp + Sb_temp;


if (Sa_temp >= 15) Sa_temp = Sa_temp+1;

Sa_temp = Sa_temp & 8'h0F;
ghi A1 (.alpha_val(Sb_temp), .Sa_temp(index));
Sx_val = Sa_temp;
Sx_exp = Sa_temp;

end //always

endmodule

==================================

is there anyone who've had a same situation?
any comment on this will be appreciated.

Thanks,
Thomas

 

[Paul Uiterlinden]

thomasc wrote:

Hi,
I'm stuck in a situation that I don't understand and need some help.

From a Verilog module, called 'abc.v', I instantiated another module,
'def.v'.
While compiling 'abc.v' using ModelSim 5.8c, I got an error message as
follows:

# ** Error: C:/ ..... abc.v(28): Undefined variable: def

You cannot instantiate a module in an always block. Put if outside the
always block.

I don't understand it because 'b.v' module is in the same project with
'abc.v' and it has passed its own testbench. and it seems that 'a.v' does
not 'know' that 'def.v' is another module. Below is abc.v file.

==================================

module abc (Sx_val, Sx_exp, Sa, Sb);

output [7:0] Sx_val, Sx_exp;

This needs to be:

output reg [7:0] Sx_val, Sx_exp;

Assignments from a procedural block (alway block in this case) can only
be done on registers.

Sa, Sb;

wire [7:0] Sa, Sb;
reg [7:0] Sa_temp, Sb_temp;
reg [7:0] alpha_table;


always @ (Sa or Sb) begin
if (Sa==0) begin
Sx_val = 8'h00;

Better to use non-blocking assignment here:

Sx_val <= 8'h00;

Please do read:
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf and
other papers on http://www.sunburst-design.com/papers/.

is there anyone who've had a same situation?
any comment on this will be appreciated.

Please get some basic Verilog knowledge first before posting to this
newsgroup.

Paul.

 

[Eyck Jentzsch]

thomasc wrote:

Hi,
I'm stuck in a situation that I don't understand and need some help.

From a Verilog module, called 'abc.v', I instantiated another module,
'def.v'.
While compiling 'abc.v' using ModelSim 5.8c, I got an error message as
follows:

# ** Error: C:/ ..... abc.v(28): Undefined variable: def

I don't understand it because 'b.v' module is in the same project with
'abc.v' and it has passed its own testbench. and it seems that 'a.v' does
not 'know' that 'def.v' is another module. Below is abc.v file.

==================================

module abc (Sx_val, Sx_exp, Sa, Sb);

output [7:0] Sx_val, Sx_exp;
input [7:0] Sa, Sb;

wire [7:0] Sa, Sb;
reg [7:0] Sa_temp, Sb_temp;
reg [7:0] alpha_table;


always @ (Sa or Sb) begin
if (Sa==0) begin
Sx_val = 8'h00;
Sx_exp = 8'h10;
end //if

else begin
if (Sb==0) begin
Sx_val = 8'h00;
Sx_exp = 8'h10;
end
end //else

def E1 (.exp_val(Sa_temp), .index(Sa));
def E2 (.exp_val(Sb_temp), .index(Sb));
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

You instantiate your modules inside of an always block so the compiler
interprets it as a variable!!

Sa_temp = Sa_temp + Sb_temp;


if (Sa_temp >= 15) Sa_temp = Sa_temp+1;

Sa_temp = Sa_temp & 8'h0F;
ghi A1 (.alpha_val(Sb_temp), .Sa_temp(index));
Sx_val = Sa_temp;
Sx_exp = Sa_temp;

end //always

endmodule

==================================

is there anyone who've had a same situation?
any comment on this will be appreciated.

Thanks,
Thomas

-Eyck