help...test bench error!

[tcl]

i had found these errors in my ModelSim :-
# ** Error: subkey_bench.vhd(25): Symbol "subkey" has already been
declared in this region.
# ** Error: subkey_bench.vhd(34): (vcom-1142) 'subkey' is an unknown
component name.
# ** Error: subkey_bench.vhd(36): Statement cannot be labeled.
# ** Error: subkey_bench.vhd(50): VHDL Compiler exiting
# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.

below is my subkey.vhd file:
------------------------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity subkey is
port (
key : in std_logic_vector(63 downto 0);
sel : in std_logic_vector(3 downto 0);
subkey : out std_logic_vector(47 downto 0)
);
end;


---------- Architecture subkey ----------
architecture simple of subkey is
signal kkey_1 : std_logic_vector(47 downto 0);
signal kkey_2 : std_logic_vector(47 downto 0);
signal kkey_3 : std_logic_vector(47 downto 0);
signal kkey_4 : std_logic_vector(47 downto 0);
signal kkey_5 : std_logic_vector(47 downto 0);
signal kkey_6 : std_logic_vector(47 downto 0);
signal kkey_7 : std_logic_vector(47 downto 0);
signal kkey_8 : std_logic_vector(47 downto 0);
signal kkey_9 : std_logic_vector(47 downto 0);
signal kkey_10 : std_logic_vector(47 downto 0);
signal kkey_11 : std_logic_vector(47 downto 0);
signal kkey_12 : std_logic_vector(47 downto 0);
signal kkey_13 : std_logic_vector(47 downto 0);
signal kkey_14 : std_logic_vector(47 downto 0);
signal kkey_15 : std_logic_vector(47 downto 0);
signal kkey_16 : std_logic_vector(47 downto 0);
signal s0_0 : std_logic_vector(47 downto 0);
signal s0_1 : std_logic_vector(47 downto 0);
signal s0_2 : std_logic_vector(47 downto 0);
signal s0_3 : std_logic_vector(47 downto 0);
signal s0_4 : std_logic_vector(47 downto 0);
signal s0_5 : std_logic_vector(47 downto 0);
signal s0_6 : std_logic_vector(47 downto 0);
signal s0_7 : std_logic_vector(47 downto 0);
signal s1_0 : std_logic_vector(47 downto 0);
signal s1_1 : std_logic_vector(47 downto 0);
signal s1_2 : std_logic_vector(47 downto 0);
signal s1_3 : std_logic_vector(47 downto 0);
signal s2_0 : std_logic_vector(47 downto 0);
signal s2_1 : std_logic_vector(47 downto 0);
signal c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,
c11x,c12x,c13x,c14x,c15x,c16x : std_logic_vector(1 to
28);
signal d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,
d11x,d12x,d13x,d14x,d15x,d16x : std_logic_vector(1 to
28);

component pc1
port (
key : in std_logic_vector(63 downto 0);
c0x,d0x : out std_logic_vector(28 downto 1)
);
end component;

component pc2
port (
c,d : in std_logic_vector(28 downto 1);
k : out std_logic_vector(48 downto 1)
);
end component;

begin
pc_1: pc1 port map ( key=>key, c0x=>c0x, d0x=>d0x );
c1x<=To_StdLogicVector(to_bitvector(c0x) rol 1);
d1x<=To_StdLogicVector(to_bitvector(d0x) rol 1);
c2x<=To_StdLogicVector(to_bitvector(c1x) rol 1);
d2x<=To_StdLogicVector(to_bitvector(d1x) rol 1);
c3x<=To_StdLogicVector(to_bitvector(c2x) rol 2);
d3x<=To_StdLogicVector(to_bitvector(d2x) rol 2);
c4x<=To_StdLogicVector(to_bitvector(c3x) rol 2);
d4x<=To_StdLogicVector(to_bitvector(d3x) rol 2);
c5x<=To_StdLogicVector(to_bitvector(c4x) rol 2);
d5x<=To_StdLogicVector(to_bitvector(d4x) rol 2);
c6x<=To_StdLogicVector(to_bitvector(c5x) rol 2);
d6x<=To_StdLogicVector(to_bitvector(d5x) rol 2);
c7x<=To_StdLogicVector(to_bitvector(c6x) rol 2);
d7x<=To_StdLogicVector(to_bitvector(d6x) rol 2);
c8x<=To_StdLogicVector(to_bitvector(c7x) rol 2);
d8x<=To_StdLogicVector(to_bitvector(d7x) rol 2);
c9x<=To_StdLogicVector(to_bitvector(c8x) rol 1);
d9x<=To_StdLogicVector(to_bitvector(d8x) rol 1);
c10x<=To_StdLogicVector(to_bitvector(c9x) rol 2);
d10x<=To_StdLogicVector(to_bitvector(d9x) rol 2);
c11x<=To_StdLogicVector(to_bitvector(c10x) rol 2);
d11x<=To_StdLogicVector(to_bitvector(d10x) rol 2);
c12x<=To_StdLogicVector(to_bitvector(c11x) rol 2);
d12x<=To_StdLogicVector(to_bitvector(d11x) rol 2);
c13x<=To_StdLogicVector(to_bitvector(c12x) rol 2);
d13x<=To_StdLogicVector(to_bitvector(d12x) rol 2);
c14x<=To_StdLogicVector(to_bitvector(c13x) rol 2);
d14x<=To_StdLogicVector(to_bitvector(d13x) rol 2);
c15x<=To_StdLogicVector(to_bitvector(c14x) rol 2);
d15x<=To_StdLogicVector(to_bitvector(d14x) rol 2);
c16x<=To_StdLogicVector(to_bitvector(c15x) rol 1);
d16x<=To_StdLogicVector(to_bitvector(d15x) rol 1);

pc2x1: pc2 port map ( c=>c1x, d=>d1x, k=>kkey_1 );
pc2x2: pc2 port map ( c=>c2x, d=>d2x, k=>kkey_2 );
pc2x3: pc2 port map ( c=>c3x, d=>d3x, k=>kkey_3 );
pc2x4: pc2 port map ( c=>c4x, d=>d4x, k=>kkey_4 );
pc2x5: pc2 port map ( c=>c5x, d=>d5x, k=>kkey_5 );
pc2x6: pc2 port map ( c=>c6x, d=>d6x, k=>kkey_6 );
pc2x7: pc2 port map ( c=>c7x, d=>d7x, k=>kkey_7 );
pc2x8: pc2 port map ( c=>c8x, d=>d8x, k=>kkey_8 );
pc2x9: pc2 port map ( c=>c9x, d=>d9x, k=>kkey_9 );
pc2x10: pc2 port map ( c=>c10x, d=>d10x, k=>kkey_10 );
pc2x11: pc2 port map ( c=>c11x, d=>d11x, k=>kkey_11 );
pc2x12: pc2 port map ( c=>c12x, d=>d12x, k=>kkey_12 );
pc2x13: pc2 port map ( c=>c13x, d=>d13x, k=>kkey_13 );
pc2x14: pc2 port map ( c=>c14x, d=>d14x, k=>kkey_14 );
pc2x15: pc2 port map ( c=>c15x, d=>d15x, k=>kkey_15 );
pc2x16: pc2 port map ( c=>c16x, d=>d16x, k=>kkey_16 );

P2 :
process(sel,kkey_1,kkey_2,kkey_3,kkey_4,kkey_5,kkey_6,kkey_7,kkey_8,kkey_9,kkey_10,kkey_11,kkey_12,kkey_13,kkey_14,kkey_15,kkey_16)
begin
if (sel(0)='0') then
s0_0 <= kkey_1;
s0_1 <= kkey_3;
s0_2 <= kkey_5;
s0_3 <= kkey_7;
s0_4 <= kkey_9;
s0_5 <= kkey_11;
s0_6 <= kkey_13;
s0_7 <= kkey_15;
else
s0_0 <= kkey_2;
s0_1 <= kkey_4;
s0_2 <= kkey_6;
s0_3 <= kkey_8;
s0_4 <= kkey_10;
s0_5 <= kkey_12;
s0_6 <= kkey_14;
s0_7 <= kkey_16;
end if;
end process;

P3 : process(sel,s0_0,s0_1,s0_2,s0_3,s0_4,s0_5,s0_6,s0_7)
begin
if (sel(1)='0') then
s1_0 <= s0_0;
s1_1 <= s0_2;
s1_2 <= s0_4;
s1_3 <= s0_6;
else
s1_0 <= s0_1;
s1_1 <= s0_3;
s1_2 <= s0_5;
s1_3 <= s0_7;
end if;
end process;

P4 : process(sel,s1_0,s1_1,s1_2,s1_3)
begin
if (sel(2)='0') then
s2_0 <= s1_0;
s2_1 <= s1_2;
else
s2_0 <= s1_1;
s2_1 <= s1_3;
end if;
end process;

P5 : process(sel,s2_0,s2_1)
begin
if (sel(3)='0') then
subkey <= s2_0;
else
subkey <= s2_1;
end if;
end process;

end simple;
---------------------------------------------------------------------------------

and these is the test bench file that i implement:-
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY subkey_bench_vhd IS
END subkey_bench_vhd;

ARCHITECTURE behavior OF subkey_bench_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT subkey
PORT(
key : IN std_logic_vector(63 downto 0);
sel : IN std_logic_vector(3 downto 0);
subkey : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL key : std_logic_vector(63 downto 0) := (others=>'0');
SIGNAL sel : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs
SIGNAL subkey : std_logic_vector(47 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: subkey PORT MAP(
key => key,
sel => sel,
subkey => subkey
);

tb : PROCESS
BEGIN

key<=x"0123456789ABCDEF";
sel<="0000";

-- Wait 100 ns for global reset to finish
wait for 100 ns;

-- Place stimulus here

wait; -- will wait forever
END PROCESS;

END;

 

[Nicolas Matringe]

tcl a écrit:

i had found these errors in my ModelSim :-
# ** Error: subkey_bench.vhd(25): Symbol "subkey" has already been
declared in this region.
# ** Error: subkey_bench.vhd(34): (vcom-1142) 'subkey' is an unknown
component name.
# ** Error: subkey_bench.vhd(36): Statement cannot be labeled.
# ** Error: subkey_bench.vhd(50): VHDL Compiler exiting
# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.

Hello
I had a look at your files: you can not give the same name to different
objects. You have a component called subkey, and a signal called
subkey.
I wouldn't have given the same name to my entity and one of its ports
either (though this seems OK because ModelSim doesn't complain)

Nicolas

 

[tcl]

Okay. I know what should I do now.
Really thanks for your help