[help]Serial Attached SCSI IP core implement with FPGA

[Dwayne Dilbeck]

I would suggest breaking the project into stages. Right now you are trying
to attack too many new items at once. I would suggest getting a good
begining verilog or Vhdl design book. Since you have experience with
programming The RTL coding should look familiar. You will just have to
get in the habit of thinking of your RTL as hardware. Keep the algorythms
simple.

second stage: Buy an FPGA starter kit. Xilinx probably has a kit for the
virtex chips. Write some simple RTL designs. IE Clock, traffic light
controller. Download them to thr fpga and learn how the fpgas and RTL
interact.

third stage: buy some books on Serial Attached SCSI. Learn what sort of
hardware should be used to make up the design. Map out which pieces you
need to write RTL code(HW) for, and which pieces you can get away with using
microcontroler code(SW) for.

Fourth stage: Start the project.


<westspeed@gmail.com> wrote in message
news:51bdd172-8d21-4f45-a139-5f846524680f@s19g2000prg.googlegroups.com...

Hi,all.I am doing a project which will implement Serial Attached SCSI
with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software
designer and
never do IC design before ,so this project is very difficult for
me.Who could help me and give me some guidances or some datum and
paper about how to implement SAS with FPGAs.I will be very
grateful.You can contact me with email.My email is
westspeed@gmail.com .Thanks very much.

 

Hi,all.I am doing a project which will implement Serial Attached SCSI
with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software
designer and
never do IC design before ,so this project is very difficult for
me.Who could help me and give me some guidances or some datum and
paper about how to implement SAS with FPGAs.I will be very
grateful.You can contact me with email.My email is
westspeed@gmail.com .Thanks very much.