[help]Serial Attached SCSI IP core implement with FPGA

[Ryan]

I think I uncovered the email thread this guy had with his boss.

--
Dear Boss,

I have put together a plan for our SAS FPGA project:

Step 1. Learn digital logic design ~4 mo
Step 2. Learn Verilog RTL design ~4 mo
Step 3. Learn hardware verification ~4 mo
Step 4. Learn SCSI ~4 mo
Step 5. Learn SAS ~4 mo
Step 6. Design it ~4 mo
Step 7. Debug it ~4 mo
Step 8. Learn Xilinx Synthesis and Place & Route Tools ~4 mo
Step 9. Test it in the lab ~4 mo

Sincerely,
Westp

--
Dear Westp,

That's 3 years! You need to find a faster solution.

Sincerely,
Boss

--
Dear Boss,

I think I have a plan...

Sincerely,
Westp


On Jan 10, 3:29 am, westsp...@gmail.com wrote:

Hi,all.I am doing a project which will implement Serial Attached SCSI
with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software
designer and
never do IC design before ,so this project is very difficult for
me.Who could help me and give me some guidances or some datum and
paper about how to implement SAS with FPGAs.I will be very
grateful.You can contact me with email.My email is
westsp...@gmail.com .Thanks very much.

 

I think this now explains the job advert I saw:

Junior designer required. Must have 5 years experience digital logic
design, Very Log RTL, hardware verification, SSCI, SSA, Zilinks
Synthesis, Root Tools. Benefits: 6-day week, free pizza after 2am.

 

Hi,all.I am doing a project which will implement Serial Attached SCSI
with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software
designer and
never do IC design before ,so this project is very difficult for
me.Who could help me and give me some guidances or some datum and
paper about how to implement SAS with FPGAs.I will be very
grateful.You can contact me with email.My email is
westspeed@gmail.com .Thanks very much.

 

[glen herrmannsfeldt]

Ryan wrote:

I think I uncovered the email thread this guy had with his boss.

I have put together a plan for our SAS FPGA project:

Step 1. Learn digital logic design ~4 mo
Step 2. Learn Verilog RTL design ~4 mo
Step 3. Learn hardware verification ~4 mo
Step 4. Learn SCSI ~4 mo
Step 5. Learn SAS ~4 mo
Step 6. Design it ~4 mo
Step 7. Debug it ~4 mo
Step 8. Learn Xilinx Synthesis and Place & Route Tools ~4 mo
Step 9. Test it in the lab ~4 mo

That's 3 years! You need to find a faster solution.

About right for a PhD project.

-- glen