Help running DDR3 simulation

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Can someone help out a VHDL guy? I am trying simulate a Micron MT41K512M16HA-107. Here is a link to the model.

https://www.micron.com/-/media/client/global/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip

The readme.txt file states "if you are using the ModelSim simulator, type "do tb.do" at the prompt" but there is no tb.do in the zip. I am trying to simulate using the following the following commands.

vlib work
vlog -sv +define+MAX_MEM +define+den8192Mb +define+sg107 +define+x16 +incdir+/. ddr3.v tb.v
vsim -novopt tb
run -all

I am getting several divide by zero errors. Here is the first.

# ** Error: (vsim-8630) tb.v(114): Infinity results from division operation..

Here is tb.v lines 112 - 114.

real tck;
wire [11:0] tccd = TCCD;
wire [11:0] tcke = max(ceil(TCKE/tck), TCKE_TCK);

Note that tck = 0 in the simulation. I believe tck is supposed to be initialized in lines 152 - 161 which has the following.

initial begin
$timeformat (-9, 1, " ns", 1);
`ifdef period
tck <= `period;
`else
tck <= ceil(TCK_MIN);
`endif
ck <= 1'b1;
odt_fifo <= 0;
end

I assume either the init code isn't being executed first or the include statements for the file that defines TCK_MIN isn't actually getting included. I have stepped through the simulation and it doesn't seem to execute the init lines. Is there something I am missing?

Thanks in advance for any help.
 
On 12/10/2019 16:47, james.w.dalton@gmail.com wrote:
Can someone help out a VHDL guy? I am trying simulate a Micron MT41K512M16HA-107. Here is a link to the model.

https://www.micron.com/-/media/client/global/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip

The readme.txt file states "if you are using the ModelSim simulator, type "do tb.do" at the prompt" but there is no tb.do in the zip. I am trying to simulate using the following the following commands.

vlib work
vlog -sv +define+MAX_MEM +define+den8192Mb +define+sg107 +define+x16 +incdir+/. ddr3.v tb.v
vsim -novopt tb
run -all

I am getting several divide by zero errors. Here is the first.

# ** Error: (vsim-8630) tb.v(114): Infinity results from division operation.
Click to expand...

vsim Message # 8630:
Evaluation of a floating point division operation involving a zero
denominator has occurred, with a result that is either positive or
negative infinity (+Inf or -Inf). This error message can be suppressed
or downgraded to a note or warning

What happens if you suppress it?

vsim -suppress 8630 tb

Note unless you run Questa -novopt is ignored by Modelsim.

Hans
www.ht-lab.com



Here is tb.v lines 112 - 114.

real tck;
wire [11:0] tccd = TCCD;
wire [11:0] tcke = max(ceil(TCKE/tck), TCKE_TCK);

Note that tck = 0 in the simulation. I believe tck is supposed to be initialized in lines 152 - 161 which has the following.

initial begin
$timeformat (-9, 1, " ns", 1);
`ifdef period
tck <= `period;
`else
tck <= ceil(TCK_MIN);
`endif
ck <= 1'b1;
odt_fifo <= 0;
end

I assume either the init code isn't being executed first or the include statements for the file that defines TCK_MIN isn't actually getting included. I have stepped through the simulation and it doesn't seem to execute the init lines. Is there something I am missing?

Thanks in advance for any help.
Click to expand...
 
On Saturday, October 12, 2019 at 12:26:28 PM UTC-4, HT-Lab wrote:
On 12/10/2019 16:47, james dalton wrote:
Can someone help out a VHDL guy? I am trying simulate a Micron MT41K512M16HA-107. Here is a link to the model.

https://www.micron.com/-/media/client/global/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip

The readme.txt file states "if you are using the ModelSim simulator, type "do tb.do" at the prompt" but there is no tb.do in the zip. I am trying to simulate using the following the following commands.

vlib work
vlog -sv +define+MAX_MEM +define+den8192Mb +define+sg107 +define+x16 +incdir+/. ddr3.v tb.v
vsim -novopt tb
run -all

I am getting several divide by zero errors. Here is the first.

# ** Error: (vsim-8630) tb.v(114): Infinity results from division operation.

vsim Message # 8630:
Evaluation of a floating point division operation involving a zero
denominator has occurred, with a result that is either positive or
negative infinity (+Inf or -Inf). This error message can be suppressed
or downgraded to a note or warning

What happens if you suppress it?

vsim -suppress 8630 tb

Note unless you run Questa -novopt is ignored by Modelsim.

Hans
www.ht-lab.com




Here is tb.v lines 112 - 114.

real tck;
wire [11:0] tccd = TCCD;
wire [11:0] tcke = max(ceil(TCKE/tck), TCKE_TCK);

Note that tck = 0 in the simulation. I believe tck is supposed to be initialized in lines 152 - 161 which has the following.

initial begin
$timeformat (-9, 1, " ns", 1);
`ifdef period
tck <= `period;
`else
tck <= ceil(TCK_MIN);
`endif
ck <= 1'b1;
odt_fifo <= 0;
end

I assume either the init code isn't being executed first or the include statements for the file that defines TCK_MIN isn't actually getting included. I have stepped through the simulation and it doesn't seem to execute the init lines. Is there something I am missing?

Thanks in advance for any help.
Click to expand...

That got me a little further. I would think that they wouldn't make the model such that you need to suppress errors. I was assuming I was missing a setting. Here is the new failure.

# tb.sdramddr3_0.file_io_open: at time 0.0 ns WARNING: no +model_data option specified, using /tmp.
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "/tmp/tb.sdramddr3_0.open_bank_file.0" for writing.
#
# No such file or directory. (errno = ENOENT) : ddr3.v(633)
# Time: 0 ps Iteration: 0 Instance: /tb/sdramddr3_0
# tb.sdramddr3_0.open_bank_file: at time 0.0 ns ERROR: failed to open /tmp/tb.sdramddr3_0.open_bank_file.0.
# ** Note: $finish : ddr3.v(637)
# Time: 0 ps Iteration: 0 Instance: /tb/sdramddr3_0
# 1
 
On 12/10/2019 18:54, James Dalton wrote:
On Saturday, October 12, 2019 at 12:26:28 PM UTC-4, HT-Lab wrote:
On 12/10/2019 16:47, james dalton wrote:
...


That got me a little further. I would think that they wouldn't make the model such that you need to suppress errors. I was assuming I was missing a setting. Here is the new failure.

# tb.sdramddr3_0.file_io_open: at time 0.0 ns WARNING: no +model_data option specified, using /tmp.
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "/tmp/tb.sdramddr3_0.open_bank_file.0" for writing.
#
# No such file or directory. (errno = ENOENT) : ddr3.v(633)
# Time: 0 ps Iteration: 0 Instance: /tb/sdramddr3_0
# tb.sdramddr3_0.open_bank_file: at time 0.0 ns ERROR: failed to open /tmp/tb.sdramddr3_0.open_bank_file.0.
# ** Note: $finish : ddr3.v(637)
# Time: 0 ps Iteration: 0 Instance: /tb/sdramddr3_0
# 1
Click to expand...

what about:

vsim -c tb +model_data+./ -do "run -all"

Regards,
Hans
www.ht-lab.com
 
On Sunday, October 13, 2019 at 3:24:23 AM UTC-4, HT-Lab wrote:
On 12/10/2019 18:54, James Dalton wrote:
On Saturday, October 12, 2019 at 12:26:28 PM UTC-4, HT-Lab wrote:
On 12/10/2019 16:47, james dalton wrote:
..


That got me a little further. I would think that they wouldn't make the model such that you need to suppress errors. I was assuming I was missing a setting. Here is the new failure.

# tb.sdramddr3_0.file_io_open: at time 0.0 ns WARNING: no +model_data option specified, using /tmp.
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "/tmp/tb.sdramddr3_0.open_bank_file.0" for writing.
#
# No such file or directory. (errno = ENOENT) : ddr3.v(633)
# Time: 0 ps Iteration: 0 Instance: /tb/sdramddr3_0
# tb.sdramddr3_0.open_bank_file: at time 0.0 ns ERROR: failed to open /tmp/tb.sdramddr3_0.open_bank_file.0.
# ** Note: $finish : ddr3.v(637)
# Time: 0 ps Iteration: 0 Instance: /tb/sdramddr3_0
# 1


what about:

vsim -c tb +model_data+./ -do "run -all"

Regards,
Hans
www.ht-lab.com
Click to expand...

That did it! Thank you.
 
On 2019-10-12 15:47:28 +0000, james.w.dalton@gmail.com said:

Can someone help out a VHDL guy? I am trying simulate a Micron
MT41K512M16HA-107. Here is a link to the model.

https://www.micron.com/-/media/client/global/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip


The readme.txt file states "if you are using the ModelSim simulator,
type "do tb.do" at the prompt" but there is no tb.do in the zip. I am
trying to simulate using the following the following commands.

vlib work
vlog -sv +define+MAX_MEM +define+den8192Mb +define+sg107 +define+x16
+incdir+/. ddr3.v tb.v
vsim -novopt tb
run -all

I am getting several divide by zero errors. Here is the first.

# ** Error: (vsim-8630) tb.v(114): Infinity results from division operation.

Here is tb.v lines 112 - 114.

real tck;
wire [11:0] tccd = TCCD;
wire [11:0] tcke = max(ceil(TCKE/tck), TCKE_TCK);

Note that tck = 0 in the simulation. I believe tck is supposed to be
initialized in lines 152 - 161 which has the following.

initial begin
$timeformat (-9, 1, " ns", 1);
`ifdef period
tck <= `period;`else
tck <= ceil(TCK_MIN);
`endif
ck <= 1'b1;
odt_fifo <= 0;
end

I assume either the init code isn't being executed first or the include
statements for the file that defines TCK_MIN isn't actually getting
included. I have stepped through the simulation and it doesn't seem to
execute the init lines. Is there something I am missing?

Thanks in advance for any help.
Click to expand...

The problem is you are using tck on line 114 before it get's
initialized in the intial begin ... end block. There are better ways to
code this to avoid the error message and not rely upon tool specific
options to skip over it. Better to code it correctly as even though you
can get modelsim/questa to ignore it you may have a down-stream tool
still error-out on it.

Thanks,
 
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