HELP, processes

H

Herr P

Guest
Why do people say then I cant write en d-latch like this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity d_latch is
port(d, clk : in std_logic;
q : out std_logic);
end d_latch;

architecture beh of d_latch is
begin
process(clk)
begin
if clk = '1' then -- check if clk went up (had a rising edge)
q <= d;
end if;
end process;
end beh;

The clk is on the sensitivity list of the process, so the process should
respond to changes on clk (also called edges), so why cant I writ it like
this?
When the process starts I know that clk had an edge, and then I test clk if
it is a '1', then I know that is was a rising edge.

Or am I wrong about sensitivity lists?

/ A beginner at VHDL
 
Hell again,, i meant flipflop when i wrote latch, sorry. But the question is
the same. :)

"Herr P" <herrp@telia.com> skrev i meddelandet news:...
Why do people say then I cant write en d-latch like this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity d_latch is
port(d, clk : in std_logic;
q : out std_logic);
end d_latch;

architecture beh of d_latch is
begin
process(clk)
begin
if clk = '1' then -- check if clk went up (had a rising edge)
q <= d;
end if;
end process;
end beh;

The clk is on the sensitivity list of the process, so the process should
respond to changes on clk (also called edges), so why cant I writ it like
this?
When the process starts I know that clk had an edge, and then I test clk
if
it is a '1', then I know that is was a rising edge.

Or am I wrong about sensitivity lists?

/ A beginner at VHDL
Click to expand...
 
"Herr P" <herrp@telia.com> wrote in message
news:mQvVb.48362$mU6.186930@newsb.telia.net...
Hell again,, i meant flipflop when i wrote latch, sorry. But the question
is
the same. :)
Click to expand...
Pepole are 100% right talking this is a latch. A FF would be

process
begin
wait until CLK = '1' -- waits until edge on CLK and CLK = '1'
Q <= D;
end process;

or

process(CLK)
begin
is CLK'event and CLK = '1' then
Q <= D;
end if;
end process;
 
"Herr P" <herrp@telia.com> schreef in bericht
news:mQvVb.48362$mU6.186930@newsb.telia.net...
architecture beh of d_latch is
begin
process(clk)
begin
if clk = '1' then -- check if clk went up (had a rising
edge)
q <= d;
end if;
end process;
end beh;

The clk is on the sensitivity list of the process, so the process should
respond to changes on clk (also called edges), so why cant I writ it
like
this?
When the process starts I know that clk had an edge, and then I test clk
if
it is a '1', then I know that is was a rising edge.

Or am I wrong about sensitivity lists?

/ A beginner at VHDL
Click to expand...
I think your understanding of the sensitivity list is correct!
Only if CLK is changed the process resumes execution. You then check if the
value of CLK is '1'.
If so you have the rising edge (assume type is BIT).

Now the problem .. if you synthesize this circuit the synthesis tool
probably can not handle such a sensitivity list.
The sysnthesis tool assumes that signal D is also in the list (maybe you get
a warning!).
But if the signal D in the list the behaviour is a latch. So the tool
generates a wrong realization.
The synthesis tool recognises a flipflop (edge sensitive devices) if it
detects 'EVENT, rising_edge etc. in the description.
Something like:
PROCESS (CLK)
BEGIN
IF rising_edge(CLK) THEN
q <=d;
END IF;
END PROCESS;

Egbert Molenkamp
 
Absolutely correct, synthesis tools think that all signals are in
sinsetivity list; therefore, you get a latch. Sinsetivity list are used by
simulations only. Seems that simulators understand this and infer identical
HW (latches). Herr, is it clear? Not for me.
 
valentin tihomirov a écrit:
"Herr P" <herrp@telia.com> wrote in message
news:mQvVb.48362$mU6.186930@newsb.telia.net...

Hell again,, i meant flipflop when i wrote latch, sorry. But the question

is

the same. :)


Pepole are 100% right talking this is a latch.
Click to expand...
Nope, it's actually a flip-flop.
A latch would be:

process(d, clk) -- d appears in the sensitivity list -> it's a latch
begin
if clk = '0' then
q <= d;
end if;
end process;


--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Hi,

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c0648d$13rujj$1@ID-212430.news.uni-berlin.de...
Absolutely correct, synthesis tools think that all signals are in
sinsetivity list; therefore, you get a latch.
Click to expand...
Agreed, as mentioned earlier (by Egbert), synthesis tools do sort of a
"pattern matching" to identify FFs and rest all will be assumedas if the
sensitivity list is complete.

Sinsetivity list are used by
simulations only. Seems that simulators understand this and infer
identical
HW (latches). Herr, is it clear? Not for me.
Click to expand...
You are correct in saying "simulators work on the basis of sensitivity
list", but the original code would simulate as a FF only (not latch). The
issue is the potential mismatch bet'n Synthesis & Simulation as Synthesis
would infer a latch in the original code. One way to avoid this confusion
would be to use:

ff_proc : process
begin
wait until rising_edge(clk);
-- code..
end process ff_proc;

This would keep both Synthesis & Simulation happy, but gets a bit tougher if
you have asynchronous reset.

HTH,
Srinivasan

--
Srinivasan Venkataramanan
Senior Verification Engineer, Intel Bangalore, India
Co-Author of: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition,
2004 isbn 0-9705394-6-0, Ben Cohen, Srinivasan & Ajeetha

http://www.noveldv.com
I don't speak for Intel
 
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