help on RISC5X RISC controller code developed by mikej

S

selva991@gmail.com

Guest
now i have the complete correct code ( i got that from open cores.org)
and i could pin point the errors im uploading the whole code
fist let me tell the errors when i compiled the code
1.in mux8 file im getting
Warning: ELAB1_0026: mux8.vhd : (87, 0): There is no default binding
for component "lut4".(No entity named "lut4" was found).
Error: COMP96_0078: mux8.vhd : (84, 22): Unknown identifier
"mux8_lut4".
Error: COMP96_0133: mux8.vhd : (84, 22): Cannot find object
declaration.
Error: COMP96_0078: mux8.vhd : (83, 22): Unknown identifier
"mux8_lut3".
Error: COMP96_0133: mux8.vhd : (83, 22): Cannot find object
declaration.
Error: COMP96_0078: mux8.vhd : (82, 22): Unknown identifier
"mux8_lut2".
Error: COMP96_0133: mux8.vhd : (82, 22): Cannot find object
declaration.

2.in mux4 file im geting
Warning: ELAB1_0026: mux4.vhd : (75, 0): There is no default binding
for component "lut4".(No entity named "lut4" was found).
Error: COMP96_0078: mux4.vhd : (72, 22): Unknown identifier
"mux8_lut2".
Error: COMP96_0133: mux4.vhd : (72, 22): Cannot find object
declaration.
Compile Architecture "RTL" of Entity "MUX4"
Compile failure 2 Errors 1 Warnings Analysis time : 0.1

3.in risc5x_xil as
warning: ELAB1_0026: risc5x_xil.vhd : (189, 0): There is no default
binding for component "ramb4_s2_s2".(No entity named "ramb4_s2_s2" was
found).

4.in add_sub
Warning: ELAB1_0026: add_sub.vhd : (76, 0): There is no default binding
for component "lut4".(No entity named "lut4" was found).
Warning: ELAB1_0026: add_sub.vhd : (90, 0): There is no default binding
for component "mult_and".(No entity named "mult_and" was found).
Warning: ELAB1_0026: add_sub.vhd : (97, 0): There is no default binding
for component "muxcy".(No entity named "muxcy" was found).
Warning: ELAB1_0026: add_sub.vhd : (105, 0): There is no default
binding for component "xorcy".(No entity named "xorcy" was found).
better the whole proram is here u ca run urself and u could debug the
errors
" http://www.opencores.net/cvsweb.shtml/risc5x/"

pls pls pls pls reply
 
selva991@gmail.com wrote:

Warning: ELAB1_0026: mux8.vhd : (87, 0): There is no default binding
for component "lut4".(No entity named "lut4" was found).
Click to expand...
Well ... this warning tells you everything you need.

It seems to me, that you have already synthesized the design. (Why?
Simulate first!) But after synthesis you did not compile the components
of your target library to your working area.

Ralf
 
actualy these were the whole components i dont find lut4 in that code
pls visist that website
 
selva991@gmail.com wrote:
actualy these were the whole components i dont find lut4 in that code
pls visist that website
Click to expand...
Did you synthesize the design? (I guess so.)

LUT = lookup table - often the name of a primitive of a FPGA

Ralf
 
selva991@gmail.com wrote:

how do i add that in the code
Click to expand...
This is the last time I will answer on such nullquotes without any
useful information, no answer to my question and not a precise
formulation of the problem!

Your FPGA vendor provides a library of all primitive cells. (The same
holds for standard cell libraries.) Compile that library. How to do this
depends on your VHDL simulator. Usually you create a new library, set it
as working library and compile the VHDL code of the target library.
After this you reset your working library to the library where your
sources code was compiled into.

I again _strongly_ recommend, that you first simulate the code, before
running synthesis!

Furthermore I recommend to learn the basics of VHDL, simulation,
synthesis and post-synthesis simulation before starting a big project.
I furthermore suggest to additionally learn how to do SDF backannotation
during post-synthesis simulation and then finally how to place & route
and how to setup your target. - All these things should be learned with
a really small and easy example, that you have to code. (Example: a
counter that is running infinitely - The MSB may be used to turn a led
on/off at a FPGA evaluation board.)

Ralf
 
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