help on a complex macro

[very_very_log]

Hi,
Can somebody explain what is m3 meant to be doing in this code?
And before that, is it a valid verilog code?

`define m1(a1,a2) a1 = a1 - a2;
`define m2(a2,a3) (a2 * a3)
`define m3(t) `" calling : `\`"m1(t)`\`"AND `\`m2(t)` \`"`"

module mod;
reg v1, v2, v3;
always begin
`m1(v1,v2);
v3 = `m2(v1,v2);
$display(`m3(v1));
end
endmodule

 

On Sep 5, 3:44 am, very_very_log <sgiitne...@gmail.com> wrote:

Hi,
Can somebody explain what is m3 meant to be doing in this code?
And before that, is it a valid verilog code?

`define m3(t)       `" calling : `\`"m1(t)`\`"AND `\`m2(t)` \`"`"

It is not valid Verilog code. It is SystemVerilog code.

The `" sequence turns into an ordinary quote after arguments have been
substituted (and presumably nested macros expanded, as this case
requires). If ordinary quotes were used, this would be a string
literal, and macro arguments and macro invocations would not be
recognized as such inside of it. This gives the same capability as
the C language macro "stringizing" operator, letting macros build
strings from pieces that include arguments.

The `\`" sequence turns into a \" in the resulting expansion. Inside
a string literal, that \" sequence means that there is a literal "
character inside the string.

The other SV macro extension is ``, which acts as a token delimiter
when looking for macro arguments, but is then discarded. This allows
you to connect the expansion of a macro argument to an identifier
without any spaces between them, building a larger identifier. This
gives the
same capability as the C language macro "token pasting" operator,
letting macros build identifiers from pieces that include arguments.