Help needed

[WahooWon]

I have to create a VHDL program that multiplies a 4-bit number by a 2
bit number to produce a 6 bit product. However, I keep getting
simulation exceptions in my with statement (see code below). Any help
to get this working would be greatly appreciated!

entity multiplier is
port(A: IN STD_LOGIC_VECTOR(1 DOWNTO 0); B: IN STD_LOGIC_VECTOR(3
downto 0); C: OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
end multiplier;

architecture mult of multiplier is
signal D,E,F: STD_LOGIC_VECTOR(5 downto 0);
signal sel: STD_LOGIC_VECTOR(1 downto 0);
begin

D <= B*"100";
E <= D srl 2;
F <= E sll 1;
--G <= "000000";

sel <= A;
with sel select
C <= "000000" when "00",
E when "01",
F when "10",
"000011" when "11";

end mult;

 

[Dave Pollum]

WahooWon wrote: I have to create a VHDL program that multiplies a 4-bit number by a 2
bit number to produce a 6 bit product.
snipped

So how about this:

entity multiplier is
port(A: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(3 downto 0);
C: OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );

architecture mult of multiplier is
begin
c <= std_logic_vector( unsigned(a) * unsigned(b) );
end mult;

-Dave Pollum

 

[Dave Pollum]

WahooWon wrote: I have to create a VHDL program that multiplies a 4-bit number by a 2
bit number to produce a 6 bit product.
rest snipped

So how about this:

entity multiplier is
port(A: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(3 downto 0);
C: OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );
end multiplier;

architecture mult of multiplier is
begin
c <= std_logic_vector( unsigned(a) * unsigned(b) );
end mult;

-Dave Pollum