Help needed for the transfer function of switched-capacitor

[andy zhu]

Hi, there

As what said on the http://www.designers-guide.com/, I design a simple
circuit for the test. It is a switch (NMOS) connected to a capacitor.
the netlist as following.

V0 (net3 0) vsource dc=0 type=sine freq=f1 ampl=1 freq2=f2 ampl2=0 \
pacmag=1 fundname="input" fundname2="input2"
V1 (net1 0) vsource type=pulse delay=250.00n val0=0 val1=2 period=Tclk \
rise=10n fall=10n width=1u fundname="clock"
C0 (net9 0) capacitor c=3f
M0 (net9 net1 net3) rn w=1.2u l=800n
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5
maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
sweeppss sweep param=f1 start=1k stop=1G dec=10 {
pss pss fund=10K harms=10 errpreset=liberal annotate=status

pac pac start=1k maxsideband=0 annotate=status
}


Here f1=10k, f2=10.1k, Tclk=10u, However, the results is not what I
expected as AC simulation results. Where I setup wrong.

If I set the f1 frequency higher, eg. 10M, it will not converge. What
should I do?

 

[Andrew Beckett]

Andym

I don't think you can have read the paper very closely, because what you're doing
seems to make little sense.

For example, you have a large signal (sine) signal input, and are sweeping that - you'd
only need to do that if you're looking to see if the mosfet is distorting - it's a slow
way of doing the simulation.

Also, you're sweeping the frequencies, but not changing the beat frequency of the
pss - if you have a 100kHz clock, and a 1kHz sine input, your pss frequency would
need to be 1k, not 10k - that's why it will have difficulty converging.

I suggest something like below would be more appropriate (note, I just
made up a model so I could run it). I didn't sweep all the way up to 1GHz (as that
slowed the simulation down), but note that I set maxacfreq on the pss because the pac
frequencies are quite high compared with the largest frequency in the pss.
As you can see, I did away with the sweep around the pss, and did the sweep
entirely in the pac - and made V0 a DC source - with pacmag left there as you
had (the other parameters on V0 are irrelevant since it is a DC source).

I suggest you go back and read the paper on designer's guide again...

Andrew.

//

parameters f1=10k f2=10.1k Tclk=10u
model rn bsim3v3 type=n vth0=0.8

V0 (net3 0) vsource dc=0 type=dc freq=f1 ampl=1 freq2=f2 ampl2=0 \
pacmag=1 fundname="input" fundname2="input2"
V1 (net1 0) vsource type=pulse delay=250.00n val0=0 val1=2 period=Tclk \
rise=10n fall=10n width=1u fundname="clock"
C0 (net9 0) capacitor c=3f
M0 (net9 net1 net3 0) rn w=1.2u l=800n
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
//sweeppss sweep param=f1 start=1k stop=1G dec=10 {
pss pss period=Tclk harms=10 errpreset=liberal annotate=status maxacfreq=10M

pac pac start=1k stop=10M dec=30 maxsideband=0 annotate=status
//}


On Thu, 01 Apr 2004 22:59:14 -0600, andy zhu <zxunyu@okstate.edu> wrote:

Hi, there

As what said on the http://www.designers-guide.com/, I design a simple
circuit for the test. It is a switch (NMOS) connected to a capacitor.
the netlist as following.

V0 (net3 0) vsource dc=0 type=sine freq=f1 ampl=1 freq2=f2 ampl2=0 \
pacmag=1 fundname="input" fundname2="input2"
V1 (net1 0) vsource type=pulse delay=250.00n val0=0 val1=2 period=Tclk \
rise=10n fall=10n width=1u fundname="clock"
C0 (net9 0) capacitor c=3f
M0 (net9 net1 net3) rn w=1.2u l=800n
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5
maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
sweeppss sweep param=f1 start=1k stop=1G dec=10 {
pss pss fund=10K harms=10 errpreset=liberal annotate=status

pac pac start=1k maxsideband=0 annotate=status
}


Here f1=10k, f2=10.1k, Tclk=10u, However, the results is not what I
expected as AC simulation results. Where I setup wrong.

If I set the f1 frequency higher, eg. 10M, it will not converge. What
should I do?

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd