L
Liang-Kai Wang
Guest
Hi,
I installed NCSU_CDK 1.4 in Fedora 3.0. I use IC 5.0.33. When I do
extract on my Layout, I see the following error message. Does this
mean I didn't install NCSU library correctly? Can NCSU 1.4 work with
Fedora 3.0 and IC 5.0.33?
thanks,
Liang-Kai
================
\o library: cla64
\o cell: cla64
\o view: layout
\o Rules come from library NCSU_TechLib_ami06.
\o Rules path is divaEXT.rul.
\o Inclusion limit is set to 1000.
\o Switches used: Extract_parasitic_caps.
\o Parsing drcExtractRules of
"/crystal/eda/cadence/local/lib/NCSU_TechLib_ami06
/divaEXT.rul"...
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "cap ivpcell
NCSU_Analog_Parts")
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "cap ivpcell
NCSU_Analog_Parts")
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor ivpcell
NCSU_Analog_
Parts")
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor ivpcell
NCSU_Analog_
Parts")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer nwell, pwell, pBulk not saved.
\o Interconnect layers merged on save: elecHighres, elecRes, polyRes,
nwellRes.
\o Interconnect layers merged on save: cp, pDiffContact,
nDiffContact, pOhmicCo
ntact, nOhmicContact, ce.
\o Interconnect layers merged on save: pDiff, nDiff, pOhmic, nOhmic.
\o
\o Errors exist in the rules file
"/crystal/eda/cadence/local/lib/NCSU_TechLib_a
mi06/divaEXT.rul".
\o Verification program terminated.
\r t
\r t
I installed NCSU_CDK 1.4 in Fedora 3.0. I use IC 5.0.33. When I do
extract on my Layout, I see the following error message. Does this
mean I didn't install NCSU library correctly? Can NCSU 1.4 work with
Fedora 3.0 and IC 5.0.33?
thanks,
Liang-Kai
================
\o library: cla64
\o cell: cla64
\o view: layout
\o Rules come from library NCSU_TechLib_ami06.
\o Rules path is divaEXT.rul.
\o Inclusion limit is set to 1000.
\o Switches used: Extract_parasitic_caps.
\o Parsing drcExtractRules of
"/crystal/eda/cadence/local/lib/NCSU_TechLib_ami06
/divaEXT.rul"...
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "cap ivpcell
NCSU_Analog_Parts")
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "cap ivpcell
NCSU_Analog_Parts")
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor ivpcell
NCSU_Analog_
Parts")
\o error: Invalid input for multiLevelParasitic(); a cap list is
expected.
\o error: Illegal input layer capacitance found in saveParasitic().
\o error: The number of entries of property list and layer list must
be the sam
e.
\o saveParasitic(capacitance "PLUS" "MINUS" "c" "pcapacitor ivpcell
NCSU_Analog_
Parts")
\o info: If short location check is desired later on, check the
saveInterconnect
\o statement for correctness:
\o Interconnect layer nwell, pwell, pBulk not saved.
\o Interconnect layers merged on save: elecHighres, elecRes, polyRes,
nwellRes.
\o Interconnect layers merged on save: cp, pDiffContact,
nDiffContact, pOhmicCo
ntact, nOhmicContact, ce.
\o Interconnect layers merged on save: pDiff, nDiff, pOhmic, nOhmic.
\o
\o Errors exist in the rules file
"/crystal/eda/cadence/local/lib/NCSU_TechLib_a
mi06/divaEXT.rul".
\o Verification program terminated.
\r t
\r t