Help need writing Single Port Block Ram in verilog

[Ajey Patil]

Hi All FPGA Gurus,

Can someone point me to verilog source to build
8bit x 16K Single Port Block Internal Ram to be used in integration
and testing of Openrisc soc on Spartan 3 LC board.

I am using Xilinx Webpack 6.2, so Core generator is
not an option.

Thanks in advance,
Regards,
AJ

 

[john jakson]

Ajey Patil <patilajeyb@netscape.net> wrote in message news:<1081664351.515136@sj-nntpcache-5>...

Hi All FPGA Gurus,

Can someone point me to verilog source to build
8bit x 16K Single Port Block Internal Ram to be used in integration
and testing of Openrisc soc on Spartan 3 LC board.

I am using Xilinx Webpack 6.2, so Core generator is
not an option.

Thanks in advance,
Regards,
AJ

Look in the templates menu, it gives Verilog/VHDL example code for
most useful structures that will be inferred from similar looking
code. For some reason it does not supply a template for a dual ported
Blockram writeable on 2 ports, only 1 so in that case I instance by
name and connect up ports, guess XST doesn't have that recognizer done
yet.

OTOH something like this in your code might help

reg [7:0] MyRam[16*1024-1:0];

....
always @(ck) if (we) MyRam <= data;

...
assign foo = MyRam[j];


regards

johnjakson_usa_com

 

[Ajey Patil]

John,
Thanks for your response, I am newbie to FPGA, so please
excuse my ignorance. If I use reg [7:0] MyRam[16*1024-1:0],
will that ensure that this ram will be allocated from Block Ram
in Spartan3 ?

I found a module in Xilinx library for 8 x 2k Block Ram
but I not sure how to extend it to build 8 x 16k, (I have a
general idea on generating EN for each block
from ADDR[14:11] , but not sure how to interface DO
and DI from all blocks )

RAMB16_S9 RAMB16_S9_inst (
.DO(DO), // 8-bit Data Output
.DOP(DOP), // 1-bit parity Output
.ADDR(ADDR), // 11-bit Address Input
.CLK(CLK), // Clock
.DI(DI), // 8-bit Data Input
.DIP(DIP), // 1-bit parity Input
.EN(EN), // RAM Enable Input
.SSR(SSR), // Synchronous Set/Reset Input
.WE(WE) // Write Enable Input
);

Any help in this regard would be highly appreciated.

Thanks,
Ajey

OTOH something like this in your code might help

reg [7:0] MyRam[16*1024-1:0];

....
always @(ck) if (we) MyRam <= data;

...
assign foo = MyRam[j];


regards

johnjakson_usa_com

 

[B. Joshua Rosen]

On Sat, 10 Apr 2004 23:21:01 -0700, Ajey Patil wrote:

Hi All FPGA Gurus,

Can someone point me to verilog source to build
8bit x 16K Single Port Block Internal Ram to be used in integration
and testing of Openrisc soc on Spartan 3 LC board.

I am using Xilinx Webpack 6.2, so Core generator is
not an option.

Thanks in advance,
Regards,
AJ

The block RAMs are available as unisim models. Look in
$XILINX/verilog/src/unisims/
The block RAMs models are,

RAMB16_S18_S18.v RAMB16_S1_S4.v RAMB16_S2_S9.v RAMB16_S4_S9.v
RAMB16_S18_S36.v RAMB16_S1_S9.v RAMB16_S2.v RAMB16_S4.v
RAMB16_S18.v RAMB16_S1.v RAMB16_S36_S36.v RAMB16_S9_S18.v
RAMB16_S1_S18.v RAMB16_S2_S18.v RAMB16_S36.v RAMB16_S9_S36.v
RAMB16_S1_S1.v RAMB16_S2_S2.v RAMB16_S4_S18.v RAMB16_S9_S9.v
RAMB16_S1_S2.v RAMB16_S2_S36.v RAMB16_S4_S36.v RAMB16_S9.v
RAMB16_S1_S36.v RAMB16_S2_S4.v RAMB16_S4_S4.v

The single port model that you want is RAMB16_S9.v

 

[john jakson]

johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0404111020.1a27558d@posting.google.com>...

Ajey Patil <patilajeyb@netscape.net> wrote in message news:<1081664351.515136@sj-nntpcache-5>...
Hi All FPGA Gurus,

Can someone point me to verilog source to build
8bit x 16K Single Port Block Internal Ram to be used in integration
and testing of Openrisc soc on Spartan 3 LC board.

I am using Xilinx Webpack 6.2, so Core generator is
not an option.

Thanks in advance,
Regards,
AJ


Look in the templates menu, it gives Verilog/VHDL example code for
most useful structures that will be inferred from similar looking
code. For some reason it does not supply a template for a dual ported
Blockram writeable on 2 ports, only 1 so in that case I instance by
name and connect up ports, guess XST doesn't have that recognizer done
yet.

OTOH something like this in your code might help

reg [7:0] MyRam[16*1024-1:0];

....
always @(ck) if (we) MyRam <= data;

...
assign foo = MyRam[j];

whoops, thatss a dual port R+W.

 

[Brian Philofsky]

Ajey Patil wrote:

John,
Thanks for your response, I am newbie to FPGA, so please
excuse my ignorance. If I use reg [7:0] MyRam[16*1024-1:0],
will that ensure that this ram will be allocated from Block Ram
in Spartan3 ?

I found a module in Xilinx library for 8 x 2k Block Ram
but I not sure how to extend it to build 8 x 16k, (I have a
general idea on generating EN for each block
from ADDR[14:11] , but not sure how to interface DO
and DI from all blocks )

Ajey,

There are two ways you can get that RAM block into your design
without Coregen. You can build it structurally or you can infer it by
describing its behavior. Each has its pluses and minuses. Inferring
the RAM will simulate faster, likely take less code to describe and will
"in theory" be more portable but you leave it up the synthesis tool to
figure out how to best map it. If you describe it structurally, what
you see is what you get and when you simulate, it should behave more
accurately to what the end result will be however it can be more wordy
to build the design this way and can make it harder to take this code
and target another device. If you want to go structurally, you were on
the right path with the HDL Template you found however if you want a
8-bit wide by 16k deep RAM, you would probably be best off using 8,
RAMB16_S1's to build the RAM. It is generally best to not mess with
addressing if you want a larger RAM than can be contained in a single
RAM Block and instead go for the deeper RAM and split up your data
signals. You could use the new Verilog-2001 generate statement (Verilog
--> Synthesis Constructs --> Generate --> Generate Multiple Instances)
to generate the 8 instances of RAM if you want to go that route and that
could save you some typing.

The other way to do this is to infer the RAM. This might be easier for
you to do so I would actually suggest you go this route unless you
prefer the structural route. If you want to learn how to infer the RAM,
that too is in the HDL Templates. If you open the template and go to:
Verilog --> Synthesis Constructs --> Common Functions --> RAM -->
BlockRAM --> Single Port, you will see three coding templates for a No
Change, Read First and Write First RAM. Choose the one that best fits
your needs, copy that code into your design and modify the signal and
parameters in there (the items listed in-between the <&gt to integrate
this into your design. That should be the easiest way to get what you
are looking for.

Good luck,

-- Brian

RAMB16_S9 RAMB16_S9_inst (
.DO(DO), // 8-bit Data Output
.DOP(DOP), // 1-bit parity Output
.ADDR(ADDR), // 11-bit Address Input
.CLK(CLK), // Clock
.DI(DI), // 8-bit Data Input
.DIP(DIP), // 1-bit parity Input
.EN(EN), // RAM Enable Input
.SSR(SSR), // Synchronous Set/Reset Input
.WE(WE) // Write Enable Input
);

Any help in this regard would be highly appreciated.

Thanks,
Ajey