help need for If statements in ALU using verilog

I was wondering if it were possible to have if statements as so for the ALU I am trying to build. I am passing values from a datapath test bench to a datapath, from the datapath into the ALU, and from the ALU back to the datapath. What i am trying to do is create a control unit which will only pass values through a certain component if the corresponding control_ALU is activated.

here is my verilog code :

module ALU (
input en_ALU, clk_ALU,
input [31:0] inputA, inputB, control_ALU,
output [31:0] resultc
);
wire [31:0] res_out;


always @(control_ALU)
begin
if(control_ALU[1]) begin
andLogic andLogic_component(
.dataA (inputA),
.dataB(inputB) ,
.resultA (res_out));
end



if(control_ALU[2]) begin
negate m0(
..inputnegate (inputA),
..resultnegate (res_out)
);
end
end

reg64bit z(.clk(clk_ALU) , .clr(clr), .enable(en_ALU), .inputd(res_out), .outputq(resultc));


endmodule

 

[GaborSzakacs]

harman0093@gmail.com wrote:

I was wondering if it were possible to have if statements as so for the ALU I am trying to build. I am passing values from a datapath test bench to a datapath, from the datapath into the ALU, and from the ALU back to the datapath. What i am trying to do is create a control unit which will only pass values through a certain component if the corresponding control_ALU is activated.

here is my verilog code :

module ALU (
input en_ALU, clk_ALU,
input [31:0] inputA, inputB, control_ALU,
output [31:0] resultc
);
wire [31:0] res_out;


always @(control_ALU)
begin
if(control_ALU[1]) begin
andLogic andLogic_component(
.dataA (inputA),
.dataB(inputB) ,
.resultA (res_out));
end



if(control_ALU[2]) begin
negate m0(
..inputnegate (inputA),
..resultnegate (res_out)
);
end
end

reg64bit z(.clk(clk_ALU) , .clr(clr), .enable(en_ALU), .inputd(res_out), .outputq(resultc));


endmodule

No. At least not for dynamic control of the path.

You need to code a multiplexer to bypass the unit. You can use
generate blocks to conditionally include an instantiation in the
design, but for that to work control_ALU needs to be a constant
and you'd need to re-synthesize if it changes. In any case, you
would need an else clause to bypass the module. For example in
your posted code, what do you expect res_out to contain if
control_ALU[2] is false?

--
Gabor

 

[unfrostedpoptart]

On Tuesday, February 24, 2015 at 7:50:54 PM UTC-8, harma...@gmail.com wrote:

here is my verilog code :

always @(control_ALU)
begin
if(control_ALU[1]) begin
andLogic andLogic_component(
.dataA (inputA),
.dataB(inputB) ,
.resultA (res_out));
end

Sorry, but you appear to have no idea how Verilog (or any HDL) works. You're trying to have hardware (e.g. andLogic) blocks dynamically get created as the circuit operates. How would that work in real hardware? You need to instantiate your modules and then use code (in always blocks or procedural statements) to control the data to and from them.

If that doesn't make sense to you then you need to get a book or google/search for an online introduction to Verilog before asking more questions here.

Good luck,

David