Help me on Configuration Statement

A

AdamS

Guest
How to use "Configuration" to select an architecture? I read
"McGraw.Hill.VHDL.Programming.by.Example.4th.Ed" but it seems not
work...

here is my code structure:

the device which should be selected:

entity PS2_CTRL
architecture A
architecture B


the entity which selects Arch.A or Arch.B

entity PS2SIMPL
architecture SCHEMATIC
component declare
component port map
end architecture

configuration sel of PS2SIMPL is
for SCHEMATIC
for PS2_CTRL_i : PS2_CTRL use entity work.ps2_ctrl(a);
end for;
end for;
end sel;

but ISE still use architecture B

can anyone tell me what's wrong? thx
 
for PS2_CTRL_i : PS2_CTRL use entity work.ps2_ctrl(a);
here ps2_ctrl should be the component_name which you declared in entity
PS2SIMPL.
I'm not sure if it's the point. but please just try to change it and to
see if it's ok

follow is the format from the vhdl language reference. hope it can help
you.


configuration configuration_name of entity_name is

-- configuration declarations
for architecture_name
for instance_label:component_name
use entity library_name.entity_name(arch_name);
end for;
-- other for clauses
end for;
 
AdamS wrote:

entity PS2_CTRL
architecture A
architecture B
Click to expand...
For the code structure above, you
will always get architecture B for the
identifier PS2_CTRL (because it is compiled last)

To specify a specific architecture, declare
a unique identifier for the entity/architecture like this:

configuration <new_identifier> of <entity_name> is
for <selected_architecture_name>
end for;
end configuration <new_identifier>;

So for your example, you might want:

configuration PS2_CTRL_B of PS2_CTRL is
for B end for;
end configuration PS2_CTRL_B


-- Mike Treseler
 
Thanks to all above--Noah and Mike Treseler.

I followed Noah to change the entity name, but it does no use. after i
change to PS2SIMPL, it even can not pass the synthesize.

and the method Mike mentioned is one that i have known. It gives any
architecture a configuration name and then select the architecture
though the configuration name.

I just want to know if the method I used can take effect? only use one
configuration in the top level to select device's architecture.
otherwise, I have to use at least three configuration statements to
select the architecture.

Thanks for your replies again.
 
Yeah, I have see this way.
But is this the only way to select the architecture? although it is
really easy to use^_^

Thanks to All Above!!

AdamS
 
I found an answer but got another question.

still use the example above:
the device is
entity PS2_CTRL
architecture A
architecture B
Click to expand...
and the top level goes like this:
entity PS2SIMPL
architecture SCHEMATIC
component declare
for PS2_CTRL_i: PS2_CRTL use entity work.ps2_ctrl(a); --this take
effect!!--
begin
component port map
end architecture

-- do not add configuration any more
only a "for" can solve the problem.



the question is:
when i use three configuration clause, it can not pass the Xilinx XST
synthesize
the error is:
-----------------------------------------------------------
FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12
21:32:28 weilin Exp $:200 - INTERNAL ERROR... while parsing
f:/sutongqi/ise/ps2_kbd_2/PS2simpl.vhd line 1. Contact your hot line.
Process will terminate. To resolve this error, please consult the
Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com
------------------------------------------------------------
It occurs when I add two configurations in the device to identify two
architecture, one configuration in the top level and a "for PS2_CTRL_i
: PS2_CTRL use configuration work.conf_A;" after component declaration.
 
I found an answer but got another question.

still use the example above:
the device is
entity PS2_CTRL
architecture A
architecture B
Click to expand...
and the top level goes like this:
entity PS2SIMPL
architecture SCHEMATIC
component declare
for PS2_CTRL_i: PS2_CRTL use entity work.ps2_ctrl(a); --this take
effect!!--
begin
component port map
end architecture

-- do not add configuration any more
only a "for" can solve the problem.



the question is:
when i use three configuration clause, it can not pass the Xilinx XST
synthesize
the error is:
-----------------------------------------------------------
FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12
21:32:28 weilin Exp $:200 - INTERNAL ERROR... while parsing
f:/sutongqi/ise/ps2_kbd_2/PS2simpl.vhd line 1. Contact your hot line.
Process will terminate. To resolve this error, please consult the
Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com
------------------------------------------------------------
It occurs when I add two configurations in the device to identify two
architecture, one configuration in the top level and a "for PS2_CTRL_i
: PS2_CTRL use configuration work.conf_A;" after component declaration.
 
I have also had difficulties when using the "configure" statement and
synthesising using XST. I found that although the syntax of a
"configure" statement parses ok its does not have the desired effect
which I suspect is a similar experience to yourself. My solution was to
not use a separate congfigure statement. I can give you an alternative
which appears to be less problematic (well with Xilinx XST):


-- VHDL module top
ARCHITECTURE behaviour OF top IS

COMPONENT dut
PORT( ... );
END COMPONENT;

-- an alternative to using a configure statement
-- to select a particular architecture
for instance1: dut use entity WORK.dut(arch_A);
for instance2: dut use entity WORK.dut(arch_B);

BEGIN
instance1: component dut
PORT MAP ( ... );

instance2: component dut
PORT MAP ( ... );

...

...
END;

-- VHDL module dut
ENTITY dut is
Port ( ... );
END dut;

ARCHITECTURE arch_A of dut is
begin
...
end arch_A;

ARCHITECTURE arch_B of dut is
begin
...
end arch_B;

-- End of VHDL



Hope this helps,

Enjoy,

Tim
 
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