help me in learning memory design

L

linuxczar

Guest
hi everybody
i have some doubts in design of memory.i am learner .let me put
it clearly
aim is to design a ROM(already some data is stored) and access data
from that to another memory.

ROM function:

module rom(data,address);
output [7:0] data;
input [5:0] address;
reg [7:0] data;
always @(address)
begin
case (address)
5'd0 : data = 8'd0 ;
5'd1 : data = 8'd1 ;
5'd2 : data = 8'd2 ;
5'd3 : data = 8'd3 ;
5'd4 : data = 8'd4 ;
5'd5 : data = 8'd5 ;
5'd6 : data = 8'd6 ;
5'd7 : data = 8'd7 ;
5'd8 : data = 8'd8 ;
5'd9 : data = 8'd9 ;
5'd10 : data = 8'd10 ;
5'd11 : data = 8'd11 ;
5'd12 : data = 8'd12 ;
5'd13 : data = 8'd13 ;
5'd14 : data = 8'd14 ;
5'd15 : data = 8'd15 ;
5'd16 : data = 8'd16 ;
5'd17 : data = 8'd17 ;
5'd18 : data = 8'd18 ;
5'd19 : data = 8'd19 ;
5'd20 : data = 8'd20 ;
5'd21 : data = 8'd21 ;
5'd22 : data = 8'd22 ;
5'd23 : data = 8'd23 ;
5'd24 : data = 8'd24 ;
5'd25 : data = 8'd25 ;
5'd26 : data = 8'd26 ;
5'd27 : data = 8'd27 ;
5'd28 : data = 8'd28 ;
5'd29 : data = 8'd29 ;
5'd30 : data = 8'd30 ;
5'd31 : data = 8'd31 ;

endcase
end
endmodule


this is working fine

now another memory which access this ROM is

module axesrom(dataout,clk);
output [7:0] dataout;
input clk;

parameter x=5'd1;
integer i,j;
reg [4:0] addr;

always@(posedge clk)
for (i=0;i<=3;i=i+1)
begin
addr=x;
for (j=0;j<=3;j=j+1)
begin
rom r1(.data(dataout),.address(addr));
addr=addr+5'd8;
end
x=x+1;
end

endmodule


OUTPUT ----------identifir "rom" not defined

can anybody tell me why i am getting this?

i am using xilinx and modelsim

thanx and regards
gkreddybh
 
linuxczar,

You can't instantiate the module inside procedural code.
See the fix below. You should typically have a read enable
or chip select to activate the ROM.

/Ed


module axesrom(dataout,clk);
output [7:0] dataout;
input clk;

parameter x=5'd1;
integer i,j;
reg [4:0] addr;

rom r1(.data(dataout),.address(addr)); //moved this line

always@(posedge clk)
for (i=0;i<=3;i=i+1)
begin
addr=x;
for (j=0;j<=3;j=j+1)
begin
addr=addr+5'd8;
end
x=x+1;
end
endmodule
 
On Mar 25, 4:37 pm, "EdA" <ed.art...@gmail.com> wrote:
linuxczar,

You can't instantiate the module inside procedural code.
See the fix below. You should typically have a read enable
or chip select to activate the ROM.

/Ed

module axesrom(dataout,clk);
output [7:0] dataout;
input clk;

parameter x=5'd1;
integer i,j;
reg [4:0] addr;

rom r1(.data(dataout),.address(addr)); //moved this line

always@(posedge clk)
for (i=0;i<=3;i=i+1)
begin
addr=x;
for (j=0;j<=3;j=j+1)
begin
addr=addr+5'd8;
end
x=x+1;
end
endmodule
Click to expand...

thanks for reply Ed/
my idea is suppose we have a ROM, in which data is stored in a
following manner.

0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31

it's like a two-dimensional data.in the above locations of ROM, data
is stored which is same address. But my wish is i want to take the one
4*4 matrix out of(in axesrom.v) this in a single clock cycle duration.
(whatever might be the duration of a clock)

Ed,
i did tried the way that u suggested what i am getting is below one

-------------System! Source file "rom.v" cannot be opened for
reading ----------


now i just used cadence verilog-XL simulator

could u plz get me out of this and if possible suggest books or
material for knowing more about "behavioral and structural mixed way
of style".
thanks and regards
linuxczar
 
On Mar 25, 11:43 am, "linuxczar" <h.264wo...@gmail.com> wrote:

thanks for reply Ed/
my idea is suppose we have a ROM, in which data is stored in a
following manner.

0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31

it's like a two-dimensional data.in the above locations of ROM, data
is stored which is same address. But my wish is i want to take the one
4*4 matrix out of(in axesrom.v) this in a single clock cycle duration.
(whatever might be the duration of a clock)

Ed,
i did tried the way that u suggested what i am getting is below one

-------------System! Source file "rom.v" cannot be opened for
reading ----------

now i just used cadence verilog-XL simulator

could u plz get me out of this and if possible suggest books or
material for knowing more about "behavioral and structural mixed way
of style".
thanks and regards
linuxczar
Click to expand...
Let's say you have 2 files axesrom.v and rom.v. I in Verilog-XL you'd
type:

% verilog axesrom.v rom.v

What command line did you use?

/Ed
 
On Mar 26, 3:42 pm, "EdA" <ed.art...@gmail.com> wrote:
On Mar 25, 11:43 am, "linuxczar" <h.264wo...@gmail.com> wrote:



thanks for reply Ed/
my idea is suppose we have a ROM, in which data is stored in a
following manner.

0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31

it's like a two-dimensional data.in the above locations of ROM, data
is stored which is same address. But my wish is i want to take the one
4*4 matrix out of(in axesrom.v) this in a single clock cycle duration.
(whatever might be the duration of a clock)

Ed,
i did tried the way that u suggested what i am getting is below one

-------------System! Source file "rom.v" cannot be opened for
reading ----------

now i just used cadence verilog-XL simulator

could u plz get me out of this and if possible suggest books or
material for knowing more about "behavioral and structural mixed way
of style".
thanks and regards
linuxczar

Let's say you have 2 files axesrom.v and rom.v. I in Verilog-XL you'd
type:

% verilog axesrom.v rom.v

What command line did you use?

/Ed
Click to expand...
yes, i had two files axesrom.v and rom.v
yeah i am using the same command
that is "verilog rom.v axesrom.v

module rom(data,address);
output [7:0] data;
input [5:0] address;
reg [7:0] data;
always @(address)
begin
case (address)
5'd0 : data = 8'd0 ;
5'd1 : data = 8'd1 ;
5'd2 : data = 8'd2 ;
5'd3 : data = 8'd3 ;
5'd4 : data = 8'd4 ;
5'd5 : data = 8'd5 ;
5'd6 : data = 8'd6 ;
5'd7 : data = 8'd7 ;
5'd8 : data = 8'd8 ;
5'd9 : data = 8'd9 ;
5'd10 : data = 8'd10 ;
5'd11 : data = 8'd11 ;
5'd12 : data = 8'd12 ;
5'd13 : data = 8'd13 ;
5'd14 : data = 8'd14 ;
5'd15 : data = 8'd15 ;
5'd16 : data = 8'd16 ;
5'd17 : data = 8'd17 ;
5'd18 : data = 8'd18 ;
5'd19 : data = 8'd19 ;
5'd20 : data = 8'd20 ;
5'd21 : data = 8'd21 ;
5'd22 : data = 8'd22 ;
5'd23 : data = 8'd23 ;
5'd24 : data = 8'd24 ;
5'd25 : data = 8'd25 ;
5'd26 : data = 8'd26 ;
5'd27 : data = 8'd27 ;
5'd28 : data = 8'd28 ;
5'd29 : data = 8'd29 ;
5'd30 : data = 8'd30 ;
5'd31 : data = 8'd31 ;

endcase
end
endmodule

//accessing rom.v
module axesrom(dataout,clk);
output [7:0] dataout;
input clk;

parameter x=5'd1;
integer i,j;
reg [5:0] addr;

rom r1(.data(dataout),.address(addr));

always@(posedge clk)
for (i=0;i<=3;i=i+1)
begin
addr=x;
for (j=0;j<=3;j=j+1)
begin

addr=addr+5'd8;
end
x=x+1;
end

endmodule

the following is the data i just stored

0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31

but i want to takeout
0 1 2 3
8 9 10 11
16 17 18 19
24 25 26 27


thanks and regards
gkreddybh
 
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