Help me converting Mathlab code to VHDL? DSPBuilder or Syst

S

Satish K

Guest
Dears

Can anybody help me in realizing below Mathlab code to VHDL
This is just a deceptive one, Tried in both DSPBuilder or
SystemGenerator.

If not possible by tool ,can anybody help me in hinting in Converting
this to VHDL.

Have many doubt's in DSPBuilder
How to insert the FOR loop in DSP Builder and Variable and
assignment's realized form it.
Thanks in advance.
Satish

---------mathlab code-------------

% Inputs : Signal : 256 Samples, 16 bits each
% constants Any value may be assigned to them for time being
% XP : 256 * 16 Bits ()
% YP : 256 * 16 Bits
% A
% B
% C
% Rmin
% Rmax
% dR
% D


% Array : array 65536*16 or block RAM

fftSig = fftshift(fft(fftshift(signal)),512));

for k = 1:256,
for k2 = 1:256
tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2);
if (tst > Rmin & tst < Rmax-dR);
IL = (tst –Rmin)/dR+1;
Ind = floor (IL);
Q =IL-Ind;
px = fftSig(Ind)+Q .*…
(fftSig(Ind+1)-fftSig(Ind));
INDEX = k + (k2 – 1)*256;
ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1)
End
End
end
--------------------------------------------
 
Try AccelChip:
http://www.accelchip.com/

Satish K wrote:

Dears

Can anybody help me in realizing below Mathlab code to VHDL
This is just a deceptive one, Tried in both DSPBuilder or
SystemGenerator.

If not possible by tool ,can anybody help me in hinting in Converting
this to VHDL.

Have many doubt's in DSPBuilder
How to insert the FOR loop in DSP Builder and Variable and
assignment's realized form it.
Thanks in advance.
Satish

---------mathlab code-------------

% Inputs : Signal : 256 Samples, 16 bits each
% constants Any value may be assigned to them for time being
% XP : 256 * 16 Bits ()
% YP : 256 * 16 Bits
% A
% B
% C
% Rmin
% Rmax
% dR
% D


% Array : array 65536*16 or block RAM

fftSig = fftshift(fft(fftshift(signal)),512));

for k = 1:256,
for k2 = 1:256
tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2);
if (tst > Rmin & tst < Rmax-dR);
IL = (tst –Rmin)/dR+1;
Ind = floor (IL);
Q =IL-Ind;
px = fftSig(Ind)+Q .*…
(fftSig(Ind+1)-fftSig(Ind));
INDEX = k + (k2 – 1)*256;
ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1)
End
End
end
--------------------------------------------
Click to expand...
 
DSP Builder is a tool which converts Simulink model (*.MDL) to VHDL.
For conversion of MATLAB m-scripts to VHDL, you have to first
translate
the matlab code to DSP Builder blocksets in Simulink. For instance,
the 'if-else' statements can be converted to mux blocks. 'For loops'
can be
converted to counters with comparators. Variables can be just plain
registers.

If you would like more examples of how to do this using DSP Builder,
please
send me an email at hneoh@altera.com

You may also want to look at AccelChip's website. They have a tool
which allows you to go directly from MATLAB code to synthesizable HDL.

Regards,
Hong Shan
hneoh@altera.com


satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0312180513.36368710@posting.google.com>...
Dears

Can anybody help me in realizing below Mathlab code to VHDL
This is just a deceptive one, Tried in both DSPBuilder or
SystemGenerator.

If not possible by tool ,can anybody help me in hinting in Converting
this to VHDL.

Have many doubt's in DSPBuilder
How to insert the FOR loop in DSP Builder and Variable and
assignment's realized form it.
Thanks in advance.
Satish

---------mathlab code-------------

% Inputs : Signal : 256 Samples, 16 bits each
% constants Any value may be assigned to them for time being
% XP : 256 * 16 Bits ()
% YP : 256 * 16 Bits
% A
% B
% C
% Rmin
% Rmax
% dR
% D


% Array : array 65536*16 or block RAM

fftSig = fftshift(fft(fftshift(signal)),512));

for k = 1:256,
for k2 = 1:256
tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2);
if (tst > Rmin & tst < Rmax-dR);
IL = (tst ?Rmin)/dR+1;
Ind = floor (IL);
Q =IL-Ind;
px = fftSig(Ind)+Q .*?
(fftSig(Ind+1)-fftSig(Ind));
INDEX = k + (k2 ? 1)*256;
ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1)
End
End
end
--------------------------------------------
Click to expand...
 
Thanks Hong Shan Neoh

1) In DSPBuilder how can we realize below equation
ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1)
2) The subsystem will be blank with input and output port only even
when we link it with the VHDL code

If you have any training material or examples which is helpful can you
forward me to my mail ID

with thanks
Satish K



hsneoh@netscape.net (Hong Shan Neoh) wrote in message news:<2ff2f33d.0312181432.5aa8ac63@posting.google.com>...
DSP Builder is a tool which converts Simulink model (*.MDL) to VHDL.
For conversion of MATLAB m-scripts to VHDL, you have to first
translate
the matlab code to DSP Builder blocksets in Simulink. For instance,
the 'if-else' statements can be converted to mux blocks. 'For loops'
can be
converted to counters with comparators. Variables can be just plain
registers.

If you would like more examples of how to do this using DSP Builder,
please
send me an email at hneoh@altera.com

You may also want to look at AccelChip's website. They have a tool
which allows you to go directly from MATLAB code to synthesizable HDL.

Regards,
Hong Shan
hneoh@altera.com


satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0312180513.36368710@posting.google.com>...
Dears

Can anybody help me in realizing below Mathlab code to VHDL
This is just a deceptive one, Tried in both DSPBuilder or
SystemGenerator.

If not possible by tool ,can anybody help me in hinting in Converting
this to VHDL.

Have many doubt's in DSPBuilder
How to insert the FOR loop in DSP Builder and Variable and
assignment's realized form it.
Thanks in advance.
Satish

---------mathlab code-------------

% Inputs : Signal : 256 Samples, 16 bits each
% constants Any value may be assigned to them for time being
% XP : 256 * 16 Bits ()
% YP : 256 * 16 Bits
% A
% B
% C
% Rmin
% Rmax
% dR
% D


% Array : array 65536*16 or block RAM

fftSig = fftshift(fft(fftshift(signal)),512));

for k = 1:256,
for k2 = 1:256
tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2);
if (tst > Rmin & tst < Rmax-dR);
IL = (tst ?Rmin)/dR+1;
Ind = floor (IL);
Q =IL-Ind;
px = fftSig(Ind)+Q .*?
(fftSig(Ind+1)-fftSig(Ind));
INDEX = k + (k2 ? 1)*256;
ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1)
End
End
end
--------------------------------------------
Click to expand...
 
I assume you want the VHDL to synthesize, if you just want to simulate
in VHDL use the real data type and translate line for line. I
also assume that for some reason you know you want custom hardware
rather than running on some general purpose computer after translaing
to C (or whatever).

If you want to build hardware then your problem is more than
just tranlating code, first you need a hardware architecture
(this might be why you are stalled). Some things to think about:

1) fft, sqrt, and exp, what algorithms will you use for these?
You might find fft IP, but for the others you probably just have
to do the work.

2) What is you required through put? how much silicon can you afford?
These might tell you if you want to unroll the loops. As an aside
unrolling would (I think) turn the sqrt and exp to constants, and
zero hardware, but you would have a *really* deep pipeline, start to
think about a few million registers (256*265*16 at a minimum).

3) What is the actual nature of the input in the real world, is it
just 256 words, or a stream or words, or blocks of 256 words? This
will infuuence your choice of architecture

4) Hardware is usually clocked, be prepared to think about where to
put registers and why. (I assume Accel Chip will do this for you)


OK, now enter your architecture in what ever method make you happy,
VHDL in a text editor, Altera/Xilinx blocks in Simulink, and so on.

Remember: programs = algorithms + data structures.
Well you have an algorithm, but you need a hardware structure.


satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0312180513.36368710@posting.google.com>...
Dears

Can anybody help me in realizing below Mathlab code to VHDL
This is just a deceptive one, Tried in both DSPBuilder or
SystemGenerator.

If not possible by tool ,can anybody help me in hinting in Converting
this to VHDL.

Have many doubt's in DSPBuilder
How to insert the FOR loop in DSP Builder and Variable and
assignment's realized form it.
Thanks in advance.
Satish

---------mathlab code-------------

% Inputs : Signal : 256 Samples, 16 bits each
% constants Any value may be assigned to them for time being
% XP : 256 * 16 Bits ()
% YP : 256 * 16 Bits
% A
% B
% C
% Rmin
% Rmax
% dR
% D


% Array : array 65536*16 or block RAM

fftSig = fftshift(fft(fftshift(signal)),512));

for k = 1:256,
for k2 = 1:256
tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2);
if (tst > Rmin & tst < Rmax-dR);
IL = (tst ?Rmin)/dR+1;
Ind = floor (IL);
Q =IL-Ind;
px = fftSig(Ind)+Q .*?
(fftSig(Ind+1)-fftSig(Ind));
INDEX = k + (k2 ? 1)*256;
ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1)
End
End
end
--------------------------------------------
Click to expand...
 
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