C
cfk
Guest
This is a Synopsys question, but I hope these sort of questions are OK here.
I have a new Synopsys installation and am trying to get my Verilog to
synthesize & simulate. My first step is to try to read and understand the
documentation. So, I go to the first diagram in the brand spanking new
Synopsys FPGA Users Guide I just got yesterday, fire off fpga_shell-t and
type 'help link_library' and get nowhere.
Of course, I launch fpga_shell without the tcl mode and 'help link_library'
works fine.
So, what is going on?
--
CK
I have a new Synopsys installation and am trying to get my Verilog to
synthesize & simulate. My first step is to try to read and understand the
documentation. So, I go to the first diagram in the brand spanking new
Synopsys FPGA Users Guide I just got yesterday, fire off fpga_shell-t and
type 'help link_library' and get nowhere.
Of course, I launch fpga_shell without the tcl mode and 'help link_library'
works fine.
So, what is going on?
--
CK