Help instantiating a megacore function

[jjlindula@hotmail.com]

Hello, I am new to Verilog and need some help instantiating a fifo in
my verilog file. Here is what I have so far.

FUNCTION lpm_fifo_dc (data[LPM_WIDTH-1..0], rdreq, wrreq, rdclock,
wrclock, aclr)
WITH (LPM_WIDTH, LPM_NUMWORDS, LPM_WIDTHU, LPM_SHOWAHEAD,
UNDERFLOW_CHECKING, OVERFLOW_CHECKING, ALLOW_RWCYCLE_WHEN_FULL,
USE_EAB, DELAY_RDUSEDW, DELAY_WRUSEDW, RDSYNC_DELAYPIPE,
WRSYNC_DELAYPIPE)

RETURNS (q[LPM_WIDTH-1..0], rdempty, rdfull, wrempty, wrfull,
rdusedw[LPM_WIDTHU-1..0], wrusedw[LPM_WIDTHU-1..0]);

module dma_mgt ( // my inputs and outputs here)


// here I instantiate the fifo
FIFIN : lpm_fifo_dc WITH (LPM_WIDTH = 64, LPM_NUMWORDS = 64,
LPM_WIDTHU = 9, RDSYNC_DELAYPIPE = 3, WRSYNC_DELAYPIPE = 3);

FIFIN.aclr = (!rstn);
FIFIN.wrclock = (clk);
FIFIN.wrreq = (wr_fiforeq);
FIFIN.data[31..0] = (dma_wrdata);
FIFIN.rdclock = (clk);
FIFIN.rdreq = (dma1_rddata);
FIFIN.q = (rd_fiforeq);


If someone could tell me what I'm doing wrong I would really
appreciate it.

Thanks,
joe