help in VHDL procedure programming

[VIPS]

Hi All

i am trying to write a procedure in VHDL which i want to generate
clock and on the rising edge of the clock i want to shift data on the
rising edge .

When i use the clause Rising_edge(clk) it is not doing anything and no
output is seen ..

Can anyone help as how to generate a clock inside the procedure and
then shift data on that clock.

I want the output of the procedure to give serial data on its
generated clock

Thanks in advance

Vipul

 

[Enes Erdin]

On 4 Şubat, 14:23, VIPS <thevipulsi...@gmail.com> wrote:

Hi All

i am trying to write a procedure in VHDL which i want to generate
clock and on the rising edge of the clock i want to shift data on the
rising edge .

When i use the clause Rising_edge(clk) it is not doing anything and no
output is seen ..

Can anyone help as how to generate a clock inside the procedure and
then shift data on that clock.

I want the output of the procedure to give serial data on its
generated clock

Thanks in advance

Vipul

Hi,

You have to indicate for which purpose you will use this procedure.
For testbench or for synthesis.

For synthesis you can not generate clocks internally as you think. You
must connect a clock pin or again generate a clock from a PLL by
connecting a "real" clock.

--enes

 

[Mike Treseler]

VIPS wrote:

i am trying to write a procedure in VHDL which i want to generate
clock and on the rising edge of the clock i want to shift data on the
rising edge .

If I want to drive a port or signal, I need
an architecture containing a parallel statement or a process.
A process contains one or more sequential statements.

A procedure could be called by this process to
provide sequential statements, but a procedure
alone cannot drive a port or signal.

For a related example, see the process tb_clk here:
http://mysite.verizon.net/miketreseler/test_uart.vhd
Notice that this process calls the procedure fixed_stim
to supply supply sequential statements for counting
and stimulus generation.

-- Mike Treseler