help in vhdl code

[rajan]

Hi,

I have a table as follows:


In0 In1 In2 In3 In4 Out1 Out2 Out3 Out4
0 0 0 1 0 o i i
i
0 1 0 1 0 i o o
i
1 1 0 0 1 * * * *



In the above truth table (In1,In2,In3,In4) are the control inputs and
(Out1, Out2, Out3, Out4) are the INOUT ports.

These outputs will be 'o', 'i' where 'o' means set as output and 'i' as
input.
'*' means dont_care.

I have come up with the following:

ARCHITECTURE example of design is

signal Out1_o : std_logic; -- INOUT port set as output
signal Out2_i : std_logic; -- INOUT port set as input
signal Out3_i : std_logic; -- INOUT port set as input
signal Out4_i : std_logic; -- INOUT port set as input
signal Out1_i : std_logic; -- INOUT port set as input
signal Out2_o : std_logic; -- INOUT port set as output
signal Out3_o : std_logic; -- INOUT port set as output

begin

all_bits <= (In0 & In1 & In2 & In3 & In4);
out_0 <= (Out1_o & Out2_i & Out3_i & Out4_i);
out_1 <= (Out1_i & Out2_o & Out3_o & Out4_i);
DONTCARE <= "UUUU";

process(all_bits)
begin
CASE all_bits is
when "00010" => output <= "out_0;
when "00010" => output <= "out_1;
when "00010" => output <= "DONTCARE;
END CASE;
end process;


Is it a correct approach. I would really appreciate your help.

Many thanks.

 

[Ralf Hildebrandt]

rajan wrote:

In the above truth table (In1,In2,In3,In4) are the control inputs and
(Out1, Out2, Out3, Out4) are the INOUT ports.
....
signal Out1_o : std_logic; -- INOUT port set as output
signal Out2_i : std_logic; -- INOUT port set as input
....
Is it a correct approach. I would really appreciate your help.

What about moving the problem one hirarchy step upward? What I mean is
the following: In your component, that uses theses ports, 3 signals must
be provided: input, output and direction control. Whithin your component
you can access this "splitted inout" very easy as each of the three
signals has only one direction.

In the upper hirarchy you have to feed these three signals to a pad
component. Ths component depends on your target library. You will find
in your library VHDL models of such pads, that can be instanced.

With this approach you design stays free from inout signals and can be
easily moved to a different target library.


Ralf