Help in SRAM block??

[dcreddy1980]

I dont know where i went wrong in the following code,when i simulate the
code...i am getting RWD <= "UUUUUU"in the waveform results....

entity SRAM is
port(CADDR : in std_logic_vector(3 downto 0);
RADDR : in std_logic_vector(6 downto 0);
RWD : inout std_logic_vector(15 downto 0);
BNKSEL : in std_logic;
RDCAS : in std_logic;
WRCAS : in std_logic;
DTRDY : out std_logic);
end SRAM;

architecture behaviour of SRAM is
begin
process(BNKSEL,RDCAS,WRCAS,CADDR,RADDR,RWD)
subtype tmp is std_logic_vector(15 downto 0);
type memory_array is array(integer range 0 to 127,integer range 0 to
15);---128 rows and 16 columns
variable mem : memory_array;
begin
if(BNKSEL'event and BNKSEL = '1') then
if(RDCAS = '1') then
RWD <=
mem(conv_integer(unsigned(CADDR)),conv_integer(unsigned(RADDR)));
DTRDY <= '1';
end if;
if(WRCAS = '1') then
mem(conv_integer(unsigned(CADDR)),conv_integer(unsigned(RADDR))) :=
RWD;
DTRDY <= '0';
end if;
end if;
end process;
end behaviour;


TESTBENCH :
------------

entity tb_SRAM is
end tb_SRAM;

architecture tb of tb_SRAM is
component SRAM
port(CADDR : in std_logic_vector(3 downto 0);
RADDR : in std_logic_vector(6 downto 0);
RWD : inout std_logic_vector(15 downto 0);
BNKSEL : in std_logic;
RDCAS : in std_logic;
WRCAS : in std_logic;
DTRDY : out std_logic);
end component;
signal RDCAS,WRCAS,DTRDY,BNKSEL : std_logic;
signal CADDR : std_logic_vector(6 downto 0);
signal RADDR : std_logic_vector(3 downto 0);
signal RWD : std_logic_vector(15 downto 0);
begin

UUT : SRAM port map(CADDR,RADDR,RWD,BNKSEL,RDCAS,WRCAS,DTRDY);

CADDR <= "0010010";
RADDR <= "0010";
RWD <= "0001000100010001";
BNKSEL <= '0','1' after 8 ns,'0' after 16 ns,'1' after 24 ns,'0' after 30
ns;
RDCAS <= '0','1' after 26 ns,'0' after 34 ns;
WRCAS <= '0','1' after 10 ns,'0' after 18 ns;

end tb;


is there any correction in my testbench???if so,can u plz rectify my
mistake....


Regards,
dcreddy1980