P
pgh
Guest
Hi:
I need a help in 2-D arrays(memories)in verilog
I have module that needs input from a testbench which is a memory
module prob(a, b,c)
output a;
input b,c;
reg [15:0] k [0:15];
reg [0:15] j;
integer count;
j=k[count];
endmodule
Test Bench
Here is the example:
module test_mod ();
reg [15:0] mem [0:15]
test M1 (a,b,c)
initial begin
readmemh("init.dat",mem);
end
Problem: I want to pass the values of mem in testbench to k in module. How
can i do that? Can i declare memory as a port and pass teh values?
I would really appreciate any kind of help
thankyou
Sari.
I need a help in 2-D arrays(memories)in verilog
I have module that needs input from a testbench which is a memory
module prob(a, b,c)
output a;
input b,c;
reg [15:0] k [0:15];
reg [0:15] j;
integer count;
j=k[count];
endmodule
Test Bench
Here is the example:
module test_mod ();
reg [15:0] mem [0:15]
test M1 (a,b,c)
initial begin
readmemh("init.dat",mem);
end
Problem: I want to pass the values of mem in testbench to k in module. How
can i do that? Can i declare memory as a port and pass teh values?
I would really appreciate any kind of help
thankyou
Sari.