help! how to resolve mismatches between pre- and post-synthe

O

owl

Guest
Hello,

As the subject. I'd like to know normally how you experts resolve the
mismatches. I'm more used to higher abstract level design, but now I'm
assigned a design with more than 100k gates and it resulted in tons of
mismatches between the pre- and post-synthesis simulations! If anybody
can give me some hint, like a link to a paper, book or website...
Thanks and bye,
Owl
 

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