help! how to pipeline a non-restoring divider in verilog

I finish the verilog coding for a non-restoring divider based gate
level. but I don't know how to pipeline it.

Could anyone help me out. thanks a lot
Jane

 

On Nov 27, 12:23 pm, jinyin...@gmail.com wrote:

I finish the verilog coding for a non-restoring divider based gate
level. but I don't know how to pipeline it.

Could anyone help me out. thanks a lot
Jane

well whenever i work on pipelining, i make the whole flow diagram on
page, go through cutset retiming, and then i simulate it. obviously,
you should be using non blocking assignment operator.

 

[vlsichipdesigner@gmail.co]

hi Umar,

nice reply, regarding optimize registers, and re-timing,
Is it possible some of your exercises or flows you can share.
In which way register re-timing and latch time-borrowing will be
different in terms of pipelining requirement???

my prayers,
chip design made easy
http://www.vlsichipdesign.com

m.umar...@gmail.com wrote:

On Nov 27, 12:23�pm, jinyin...@gmail.com wrote:
I finish the verilog coding for a non-restoring divider based gate
level. but I don't know how to pipeline it.

Could anyone help me out. thanks a lot
Jane



well whenever i work on pipelining, i make the whole flow diagram on
page, go through cutset retiming, and then i simulate it. obviously,
you should be using non blocking assignment operator.