HELP FRO MEMORY MODELING

L

linuxczar

Guest
I AM NOT GETTING ANYOUTPUT FOR THE FOLLOWING PROGRAM AND ASSOCIATED
TESTBENCH . COULD ANY ONE DRAG ME OUTOF THIS PLZZ?
I JUST ATTATCHED SRAM.V AND IT'S TESTBENCH AND OUTPUT IN CADENCE
VERILOG-XL.
//module for SRAM single port
module sram(dataout,datain,address,enable,readwrite);
output [7:0] dataout;
input [7:0] datain;
input enable;
input readwrite;
input [7:0] address;

reg [7:0] dataout;

reg [7:0] memory [79:0];

always@( enable)

if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

endmodule


//testbench for sram.v
module sram_tb;
reg [7:0] datain;
reg enable;
reg readwrite;
reg [7:0] address;
wire [7:0] dataout;

sram s1(dataout,datain,address,enable,readwrite);

initial
begin
$monitor($time,"enable=%b,readwrite=%b,address=%d,---,datain=
%d,dataout=%d",enable,readwrite,address,datain,dataout);
end

initial
begin
enable=0;readwrite=0;address=8'd0;datain=8'd0;
end

initial
begin
#5 enable=1'b1;readwrite=1'b0;address=8'd0;datain=8'd22;
#5 enable=1'b1;readwrite=1'b1;address=8'd0;
#5 enable=1'b1;readwrite=1'b0;address=8'd1;datain=8'd12;
#5 enable=1'b1;readwrite=1'b1;address=8'd1;
end

initial
begin
$recordfile("sram.trn");
$recordvars();
end

endmodule

the following output iam getting in CADENCE VERILOG-XL SIMULATOR

Compiling source file "sram.v"
Compiling source file "sram_tb.v"
Highest level modules:
sram_tb

0enable=0,readwrite=0,address= 0,---,datain=
0,dataout= x
5enable=1,readwrite=0,address= 0,---,datain=
22,dataout= x
10enable=1,readwrite=1,address= 0,---,datain=
22,dataout= x
15enable=1,readwrite=0,address= 1,---,datain=
12,dataout= x
20enable=1,readwrite=1,address= 1,---,datain=
12,dataout= x
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.1 secs to link + 0.1 secs in
simulation
End of Tool: VERILOG-XL 05.60.001-p Mar 14, 2007 14:29:59

THANKS AND REGARDS
GKREDDYBH.
 
On 14 Mar 2007 02:06:46 -0700, "linuxczar" <h.264world@gmail.com>
wrote:

I AM NOT GETTING ANYOUTPUT FOR THE FOLLOWING PROGRAM
Click to expand...
Not only are you shouting, you're lying too - the output is just what
I would expect it to be, and you've shown it!

//module for SRAM single port
module sram(dataout,datain,address,enable,readwrite);
[...]
always@( enable)
Click to expand...
Are you *sure* this is the sensitivity list you require?
Does your memory *really* do interesting things both
on the rising and the falling edge of enable, and at
no other times? I would have a very hard time
designing a piece of electronics to work like that.

if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;
Click to expand...
OK, so on every transition of enable, you do a write into memory[]
if the value of readwrite is zero.

And then your testbench goes on to create just one transition of
enable (at time 5, first statement in your second initial block),
and you are changing datain at exactly the same time. That sounds
like a race to me.

Sketch out some interface waveforms, decide what should happen
at each step, and then ensure that your model respects that.

If you have edge-sensitive behaviour, consider ensuring that
all other signals have a reasonable amount of setup and hold
time relative to that edge.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On 3ÔÂ14ČŐ, ĎÂÎç5Ęą06ˇÖ, "linuxczar" <h.264wo...@gmail.com> wrote:
I AM NOT GETTING ANYOUTPUT FOR THE FOLLOWING PROGRAM AND ASSOCIATED
TESTBENCH . COULD ANY ONE DRAG ME OUTOF THIS PLZZ?
I JUST ATTATCHED SRAM.V AND IT'S TESTBENCH AND OUTPUT IN CADENCE
VERILOG-XL.
//module for SRAM single port
module sram(dataout,datain,address,enable,readwrite);
output [7:0] dataout;
input [7:0] datain;
input enable;
input readwrite;
input [7:0] address;

reg [7:0] dataout;

reg [7:0] memory [79:0];

always@( enable)

if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

endmodule

//testbench for sram.v
module sram_tb;
reg [7:0] datain;
reg enable;
reg readwrite;
reg [7:0] address;
wire [7:0] dataout;

sram s1(dataout,datain,address,enable,readwrite);

initial
begin
$monitor($time,"enable=%b,readwrite=%b,address=%d,---,datain> %d,dataout=%d",enable,readwrite,address,datain,dataout);
end

initial
begin
enable=0;readwrite=0;address=8'd0;datain=8'd0;
end

initial
begin
#5 enable=1'b1;readwrite=1'b0;address=8'd0;datain=8'd22;
#5 enable=1'b1;readwrite=1'b1;address=8'd0;
#5 enable=1'b1;readwrite=1'b0;address=8'd1;datain=8'd12;
#5 enable=1'b1;readwrite=1'b1;address=8'd1;
end

initial
begin
$recordfile("sram.trn");
$recordvars();
end

endmodule

the following output iam getting in CADENCE VERILOG-XL SIMULATOR

Compiling source file "sram.v"
Compiling source file "sram_tb.v"
Highest level modules:
sram_tb

0enable=0,readwrite=0,address= 0,---,datain> 0,dataout= x
5enable=1,readwrite=0,address= 0,---,datain> 22,dataout= x
10enable=1,readwrite=1,address= 0,---,datain> 22,dataout= x
15enable=1,readwrite=0,address= 1,---,datain> 12,dataout= x
20enable=1,readwrite=1,address= 1,---,datain> 12,dataout= x
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.1 secs to link + 0.1 secs in
simulation
End of Tool: VERILOG-XL 05.60.001-p Mar 14, 2007 14:29:59

THANKS AND REGARDS
GKREDDYBH.
Click to expand...
always@( enable or readwrite or datain)
if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

try that and it will go well.
 
On 3ÔÂ14ČŐ, ĎÂÎç5Ęą06ˇÖ, "linuxczar" <h.264wo...@gmail.com> wrote:
I AM NOT GETTING ANYOUTPUT FOR THE FOLLOWING PROGRAM AND ASSOCIATED
TESTBENCH . COULD ANY ONE DRAG ME OUTOF THIS PLZZ?
I JUST ATTATCHED SRAM.V AND IT'S TESTBENCH AND OUTPUT IN CADENCE
VERILOG-XL.
//module for SRAM single port
module sram(dataout,datain,address,enable,readwrite);
output [7:0] dataout;
input [7:0] datain;
input enable;
input readwrite;
input [7:0] address;

reg [7:0] dataout;

reg [7:0] memory [79:0];

always@( enable)

if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

endmodule

//testbench for sram.v
module sram_tb;
reg [7:0] datain;
reg enable;
reg readwrite;
reg [7:0] address;
wire [7:0] dataout;

sram s1(dataout,datain,address,enable,readwrite);

initial
begin
$monitor($time,"enable=%b,readwrite=%b,address=%d,---,datain> %d,dataout=%d",enable,readwrite,address,datain,dataout);
end

initial
begin
enable=0;readwrite=0;address=8'd0;datain=8'd0;
end

initial
begin
#5 enable=1'b1;readwrite=1'b0;address=8'd0;datain=8'd22;
#5 enable=1'b1;readwrite=1'b1;address=8'd0;
#5 enable=1'b1;readwrite=1'b0;address=8'd1;datain=8'd12;
#5 enable=1'b1;readwrite=1'b1;address=8'd1;
end

initial
begin
$recordfile("sram.trn");
$recordvars();
end

endmodule

the following output iam getting in CADENCE VERILOG-XL SIMULATOR

Compiling source file "sram.v"
Compiling source file "sram_tb.v"
Highest level modules:
sram_tb

0enable=0,readwrite=0,address= 0,---,datain> 0,dataout= x
5enable=1,readwrite=0,address= 0,---,datain> 22,dataout= x
10enable=1,readwrite=1,address= 0,---,datain> 22,dataout= x
15enable=1,readwrite=0,address= 1,---,datain> 12,dataout= x
20enable=1,readwrite=1,address= 1,---,datain> 12,dataout= x
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.1 secs to link + 0.1 secs in
simulation
End of Tool: VERILOG-XL 05.60.001-p Mar 14, 2007 14:29:59

THANKS AND REGARDS
GKREDDYBH.
Click to expand...
always@( enable or readwrite or datain)
if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

try that and it will go well.
 
On Mar 14, 5:08 pm, "Homuncilus" <Sha.Cr...@gmail.com> wrote:
On 3月14日, 下午5时06分, "linuxczar" <h.264wo...@gmail.com> wrote:



I AM NOT GETTING ANYOUTPUT FOR THE FOLLOWING PROGRAM AND ASSOCIATED
TESTBENCH . COULD ANY ONE DRAG ME OUTOF THIS PLZZ?
I JUST ATTATCHED SRAM.V AND IT'S TESTBENCH AND OUTPUT IN CADENCE
VERILOG-XL.
//module for SRAM single port
module sram(dataout,datain,address,enable,readwrite);
output [7:0] dataout;
input [7:0] datain;
input enable;
input readwrite;
input [7:0] address;

reg [7:0] dataout;

reg [7:0] memory [79:0];

always@( enable)

if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

endmodule

//testbench for sram.v
module sram_tb;
reg [7:0] datain;
reg enable;
reg readwrite;
reg [7:0] address;
wire [7:0] dataout;

sram s1(dataout,datain,address,enable,readwrite);

initial
begin
$monitor($time,"enable=%b,readwrite=%b,address=%d,---,datain> > %d,dataout=%d",enable,readwrite,address,datain,dataout);
end

initial
begin
enable=0;readwrite=0;address=8'd0;datain=8'd0;
end

initial
begin
#5 enable=1'b1;readwrite=1'b0;address=8'd0;datain=8'd22;
#5 enable=1'b1;readwrite=1'b1;address=8'd0;
#5 enable=1'b1;readwrite=1'b0;address=8'd1;datain=8'd12;
#5 enable=1'b1;readwrite=1'b1;address=8'd1;
end

initial
begin
$recordfile("sram.trn");
$recordvars();
end

endmodule

the following output iam getting in CADENCE VERILOG-XL SIMULATOR

Compiling source file "sram.v"
Compiling source file "sram_tb.v"
Highest level modules:
sram_tb

0enable=0,readwrite=0,address= 0,---,datain> > 0,dataout= x
5enable=1,readwrite=0,address= 0,---,datain> > 22,dataout= x
10enable=1,readwrite=1,address= 0,---,datain> > 22,dataout= x
15enable=1,readwrite=0,address= 1,---,datain> > 12,dataout= x
20enable=1,readwrite=1,address= 1,---,datain> > 12,dataout= x
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.1 secs to link + 0.1 secs in
simulation
End of Tool: VERILOG-XL 05.60.001-p Mar 14, 2007 14:29:59

THANKS AND REGARDS
GKREDDYBH.

always@( enable or readwrite or datain)
if (readwrite)
dataout <= memory[address];
else
memory[address]<=datain;

try that and it will go well.
Click to expand...
it worked
thank you

regards
gkreddy.bh
 
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