Help for a verilog syntax

[Qingbo]

Hi,

I am given a testbench, and was asked to write the module. However I
don't know a syntax they used in the testbench. Can someone help me on
this? The part of testbench is posted below.

The "UUT.M" is obviously an array of data, but my question is how
should the M be defined in the decoder7 module. Should it be the same
array as M_local_tb, or a reg, or other kind of data types. Please
give me a pointer if you know.

Thank you in advance,


===============================================
decoder7 UUT (Start_tb, Ack_tb, Clk_tb, Reset_tb, res_tb);

task memory_initialization;
input [127:0] M_local_tb;
integer i, j;
begin
for (i=0; i<=15; i = i +1)
for (j=0; j<=7; j = j +1)
UUT.M[j] = M_local_tb[(i*8)+j];
end
endtask
============================================

 

[Jonathan Bromley]

On Tue, 7 Apr 2009 02:46:55 -0700 (PDT), Qingbo wrote:

I am given a testbench, and was asked to write the module.

Are there some Extreme Programmers in your organization?

The "UUT.M" is obviously an array of data, but my question is how
should the M be defined in the decoder7 module.
===============================================
decoder7 UUT (Start_tb, Ack_tb, Clk_tb, Reset_tb, res_tb);

task memory_initialization;
input [127:0] M_local_tb;
integer i, j;
begin
for (i=0; i<=15; i = i +1)
for (j=0; j<=7; j = j +1)
UUT.M[j] = M_local_tb[(i*8)+j];
end
endtask
============================================

It's clear that UUT.M is a Verilog "memory", in other
words an array of vectors. Within the module you
might declare it something like this:

module decoder7(.....);
reg [7:0] M [0:15]; // array of 16 vectors, each 8 bits
...

I guessed the subscript ranges by looking at the loop,
which splits your 128-bit vector "M_local_tb" into
16 slices each of 8 bits. It's done this way because
you can't pass such a memory as an argument to a task
(although you *can* do so in SystemVerilog). To pass
such a 16x8-bit value as a task argument or through
a port, you must flatten it to a 128-bit vector.

By the way: the testbench is clearly using Verilog-2001
or later syntax, since the double subscript
UUT.M[j]
is illegal in Verilog-1995. So it would probably be
neater to use Verilog-2001 indexed part select to
slice the 128-bit vector:

for (i=0; i<16; i=i+1)
UUT.M = M_local_tb[8*i +: 8];

Hope this helps
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

On 8 אפריל, 00:04, Jonathan Bromley <jonathan.brom....@MYCOMPANY.com>
wrote:

On Tue, 7 Apr 2009 02:46:55 -0700 (PDT), Qingbo wrote:
I am given a testbench, and was asked to write the module.

Are there some Extreme Programmers in your organization?

The "UUT.M" is obviously an array of data, but my question is how
should the M be defined in the decoder7 module.
==============================================> >decoder7 UUT (Start_tb, Ack_tb, Clk_tb, Reset_tb, res_tb);

task memory_initialization;
input [127:0] M_local_tb;
integer i, j;
begin
for (i=0; i<=15; i = i +1)
for (j=0; j<=7; j = j +1)
UUT.M[j] = M_local_tb[(i*8)+j];
end
endtask
===========================================
It's clear that UUT.M is a Verilog "memory", in other
words an array of vectors. Within the module you
might declare it something like this:

module decoder7(.....);
reg [7:0] M [0:15]; // array of 16 vectors, each 8 bits
...

I guessed the subscript ranges by looking at the loop,
which splits your 128-bit vector "M_local_tb" into
16 slices each of 8 bits. It's done this way because
you can't pass such a memory as an argument to a task
(although you *can* do so in SystemVerilog). To pass
such a 16x8-bit value as a task argument or through
a port, you must flatten it to a 128-bit vector.

By the way: the testbench is clearly using Verilog-2001
or later syntax, since the double subscript
UUT.M[j]
is illegal in Verilog-1995. So it would probably be
neater to use Verilog-2001 indexed part select to
slice the 128-bit vector:

for (i=0; i<16; i=i+1)
UUT.M = M_local_tb[8*i +: 8];

Hope this helps
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Please see an example at
http://bknpk.no-ip.biz/MiscellaneousHW/regFIFO.html
The following is a small design of a FIFO, which is built of Flip-Flop
devices. I found the design some where on the web, fixed some bugs,
created a test bench to test it and PERL script to automate the
testing. This site will demonstrate all of the three.

 

[Qingbo]

Thank you very much to you all!