Help for 4th order runge-kutta VHDL implementation

[Guido]

Hi all!
I was wondering if some of you could suggest me some document where I
can find help in implementing a 4th order Runge-Kutta method on FPGA in
VHDL.
Relying on you I send you all my greetings
Guido

 

[Ben Jones]

Hi,

I was wondering if some of you could suggest me some document where I
can find help in implementing a 4th order Runge-Kutta method on FPGA in
VHDL.

Why don't you try it, and tell us where you get stuck?

-Ben-

 

Guido wrote:

Hi all!
I was wondering if some of you could suggest me some document where I
can find help in implementing a 4th order Runge-Kutta method on FPGA in
VHDL.
BTW, have you implemented the second order? Because then the fourth

order method follows a bit directly.

Relying on you I send you all my greetings
Guido
Just some pointers to solution of your problem. The Runge Kutta Method

requires calculation of k-values. So you must have a set of addres and
dividers to achieve the final step of caluclation y(n+1). The previous
step to this is the caluclation of k-values. In my first opinion, that
hardware would be fixed as it depends on the kind of differential eqn
you want to integrate. You should store the outputs and reuse them for
the next cycle. You can have a comparator to choose check the accuracy.