Help! ECO in Silicon Ensemble ~~

[sunkey]

We want to do a 'metal-revision' on a chip, that's means , only metal
layers can be changed and other layer (such as diffusion or poly etc)
should be keeped excactly where there were.

My strategy is run the ECO routing on the database which were placed
already ( the cells are solid and settled-down) , and it works well. But
on big-problems is, we want use some 'spare-cell/dummy-cell' to change our
logic, which were placed in the design already. and is there any way for SE
to recoginze these dummy-cells automatically and change the routing to
them(for no any cell can be added) ?? Or we need to edit the Verilog
netlist to re-define the pin/conenction one by one, which will take so
much time .. ( for all dummy cell was dfined a s 'module', which contains
a set of basic logic device with input to ground, output floating) .

is there any one can give me help? thx a lot!

 

[m]

On Tue, 23 Aug 2005 23:08:46 -0400, "sunkey" <sunkey@263.net> wrote:

We want to do a 'metal-revision' on a chip, that's means , only metal
layers can be changed and other layer (such as diffusion or poly etc)
should be keeped excactly where there were.

My strategy is run the ECO routing on the database which were placed
already ( the cells are solid and settled-down) , and it works well. But
on big-problems is, we want use some 'spare-cell/dummy-cell' to change our
logic, which were placed in the design already. and is there any way for SE
to recoginze these dummy-cells automatically and change the routing to
them(for no any cell can be added) ?? Or we need to edit the Verilog
netlist to re-define the pin/conenction one by one, which will take so
much time .. ( for all dummy cell was dfined a s 'module', which contains
a set of basic logic device with input to ground, output floating) .

is there any one can give me help? thx a lot!

Unfortunately in SE there is no way to add new cells and have it map
them to spare cells. You have to do exactly what you don't want to do.
You have to generate a new verilog netlist which reconnects existing
cells to implement the logic change you want and do a "input verilog
eco" followed by a wroute. Don't use incremental route option though.
Wroute is smart enough to figure out which routes need changed.

One thing you have to pay attention is to keep the existing hierarchy
in your design, ie if you need to change logic in a lower level
module, you need to bring the nets to where the spares are, not move
the spares across modules.

With Encounter, doing ECOs is a little bit easier. You can generate
your new logic in gate level (which is still needed of course) and
then you can get SOCE to map the new cells to the closest spares (or
any cells you define as spare with specifysparegate (?)). If you
define your spares with some thought (I only have 2x nand2, nors,
inverters and buffers) you can restrict your synthesis to this subset
and get the synthesis tool to map your new rtl to gates then you drop
the new gates to your design and SOCE finds the closest "spares" to
use. It is pretty neat.

 

[sunkey]

Thanks a lot ~~ seems we need to upgrade to the SOC encounter a.s.a.p ~

and excaclty , the 'wroute increment' will make some strange thing ( or
do nothing ) after the eco verilog in, but 'wroute' will do that very well
... -__-

and we figure out a 'poor' way to do the 'spare-cell-recoginze' that is,
we modified the DEF file which exported after the 'placed' done database,
and delete the cell in the def which were spare-cells and change them to
the instence name we need to do ECO ..
also it's looks not smart enough. but..it works.

thanks again~~