help:dual-edge flip-flop possible using Verilog?

[yyqonline]

Im designing a module working as an fm0-encoder, the clk and max
datarate of which are both 640KHz. It is not complicated when the
datarate is lower than 320K, the half of clk. But when the datarate of
640K, the clk frequency, is concerned, the problem comes that I have to
change the state at both the rising and falling edge of the clk. Now I
am using a mothod via combinational output, which is not so good and
expansible as registered output using an FSM. I think that an FSM using
DET(dual-edge flip-flop) would work, but I am not sure wether it is
recommandable to use det and I don't know how to describe a det using
synthesizable Verilog?
It would be appreciated very much if some of you can
*comments about the det method,
*the methed about how to describe a det flip-flop

thans a lot for any help!

 

hi i don't use such FF's but i would try

always @ ( posedge clk or negedge clk ) begin

my_flip_flop <= my_flip_flop_nxt ;

end

maybe this what you need, but i am not sure if any synthesis tool or
librarie can live with it.