R
Reza Naima
Guest
So I'm a newbie to DPL, though I'm experienced w/ microcontrollers. I
wrote code for a CPLD (xilinx target, though it can change if needed)
that is supposed to run an A2D at high speed, communicate via SPI, and
take the data and convert it to a manchester-encoded stream and output
that. It seems to work fine in the simulator that I'm using (a trial
version of silos came with the veriolog book I bought), but I'm getting
warning with xilinx webpack. Also, when I run the synthesize option,
it never finishes - just sits there spinning for awhile. I'm using the
6.3v of webpack as that's the version that works with the programmer I
have, but I'm tempted to insall 7.0 just to see if that works any
better. I'll proivde the errors I get, followed by a copy of the code
I wrote. The clock (clk) is supposed externally generated, though I'm
not sure how to implement it other than the way I did. I also rely
heavily on delays in sending out the initalization strings - I'm not
sure how it'll be implemented in the CPLD. There are only 64 flipflops
in the target cpld that I want to use, so storing the init strings in
flip-flop memory seemed wasteful.
Any help, or pointers to good docs would be great!
Thanks in advance,
Reza
Analyzing top module <a2d>.
WARNING:Xst:854 - a2d.v line 22: Ignored initial statement.
WARNING:Xst:916 - a2d.v line 32: Delay is ignored for synthesis.
WARNING:Xst:854 - a2d.v line 35: Ignored initial statement.
WARNING:Xst:916 - a2d.v line 47: Delay is ignored for synthesis.
WARNING:Xst:905 - a2d.v line 44: The signals <outClock> are missing in
the sensitivity list of always block.
WARNING:Xst:916 - a2d.v line 58: Delay is ignored for synthesis.
WARNING:Xst:916 - a2d.v line 59: Delay is ignored for synthesis.
WARNING:Xst:916 - a2d.v line 60: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each
module.
module a2d(sck,dout,din,cs,tx);
output sck;
output dout;
input din;
output cs;
output tx;
reg [31:0] wData = 0 ;
reg wPointer;
reg sck;
reg dout;
reg cs;
reg tx;
reg clk;
reg outClock = 0;
reg init;
reg [3:0] bit;
reg [3:0] bit2;
initial begin
clk = 0;
sck = 1;
wPointer = 0;
#10 init = 1;
$monitor("data=",wData[3:0]);
end
/* TEST CLOCK */
always
#1 clk = ~clk;
initial begin
cs <= 1;
dout <= 0;
tx <= 0;
#1500 $finish;
end
/* GENERATE SCK WHEN outClock HIGH */
/* SCK = CLOCK/8 */
always @(clk) begin
if (outClock == 1) begin
sck = !sck;
#4;
end else
sck = 1;
end
/* SENT INIT ROUTINE */
always @(posedge init) begin
dout = 1;
/* FIRST DUMMY WORD */
cs = 0;
#4 outClock = 1;
#124 outClock = 0;
#4 cs = 1;
/* SECOND DUMMY WORD */
#16 cs = 0;
#4 outClock = 1;
#124 outClock = 0;
#4 cs = 1;
/* CONFIGURATION PARAMETERS */
#16 cs = 0;
#4 outClock = 1;
#76 dout = 0;
#8 dout = 1;
#42 outClock = 0;
#2 cs = 1;
#8 init = 0;
end
// CYCLE DATA AQUISITION AFTER INIT FINISHED
always @(negedge init) begin
#2 cs = 0;
#2 outClock = 1;
while (1) begin
wData[(16*wPointer)] = din;
/* test*/
bit =1 ;
repeat(15) begin
bit = bit + 1;
/* endtest */
// for (bit=1; bit>0; bit = bit + 1 ) begin
#4 wData[(16*wPointer)+bit] = din;
#4;
end
#8 wPointer = wPointer + 1;
cs = 1;
#4 cs = 0;
#4;
end
end
// MANCHESTER ENCODING
always @(posedge wPointer) begin
if (wData[3] || wData[2] || wData[1] || wData[0])
wData[0] = 0;
else
wData[1] = 1;
wData[1] = ^wData[15:4];
wData[2] = ^wData[15:10];
wData[3] = ^wData[9:4];
tx=0;
bit2=0;
repeat(16) begin
if (wData[bit2] == 1) begin
tx=1;
#4 tx=0;
#4;
end else begin
tx = 0;
#4 tx = 1;
#4;
end
bit2 = bit2 + 1;
end
tx=0;
end
always @(negedge wPointer) begin
if (wData[19] || wData[18] || wData[17] || wData[16])
wData[16] = 0;
else
wData[16] = 1;
wData[1] = ^wData[31:20];
wData[2] = ^wData[31:26];
wData[3] = ^wData[25:20];
tx=0;
bit2=0;
repeat(16) begin
if (wData[bit2+16] == 1) begin
tx=1;
#4 tx=0;
#4;
end else begin
tx = 0;
#4 tx = 1;
#4;
end
bit2 = bit2 + 1;
end
tx=0;
end
endmodule
wrote code for a CPLD (xilinx target, though it can change if needed)
that is supposed to run an A2D at high speed, communicate via SPI, and
take the data and convert it to a manchester-encoded stream and output
that. It seems to work fine in the simulator that I'm using (a trial
version of silos came with the veriolog book I bought), but I'm getting
warning with xilinx webpack. Also, when I run the synthesize option,
it never finishes - just sits there spinning for awhile. I'm using the
6.3v of webpack as that's the version that works with the programmer I
have, but I'm tempted to insall 7.0 just to see if that works any
better. I'll proivde the errors I get, followed by a copy of the code
I wrote. The clock (clk) is supposed externally generated, though I'm
not sure how to implement it other than the way I did. I also rely
heavily on delays in sending out the initalization strings - I'm not
sure how it'll be implemented in the CPLD. There are only 64 flipflops
in the target cpld that I want to use, so storing the init strings in
flip-flop memory seemed wasteful.
Any help, or pointers to good docs would be great!
Thanks in advance,
Reza
Analyzing top module <a2d>.
WARNING:Xst:854 - a2d.v line 22: Ignored initial statement.
WARNING:Xst:916 - a2d.v line 32: Delay is ignored for synthesis.
WARNING:Xst:854 - a2d.v line 35: Ignored initial statement.
WARNING:Xst:916 - a2d.v line 47: Delay is ignored for synthesis.
WARNING:Xst:905 - a2d.v line 44: The signals <outClock> are missing in
the sensitivity list of always block.
WARNING:Xst:916 - a2d.v line 58: Delay is ignored for synthesis.
WARNING:Xst:916 - a2d.v line 59: Delay is ignored for synthesis.
WARNING:Xst:916 - a2d.v line 60: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each
module.
module a2d(sck,dout,din,cs,tx);
output sck;
output dout;
input din;
output cs;
output tx;
reg [31:0] wData = 0 ;
reg wPointer;
reg sck;
reg dout;
reg cs;
reg tx;
reg clk;
reg outClock = 0;
reg init;
reg [3:0] bit;
reg [3:0] bit2;
initial begin
clk = 0;
sck = 1;
wPointer = 0;
#10 init = 1;
$monitor("data=",wData[3:0]);
end
/* TEST CLOCK */
always
#1 clk = ~clk;
initial begin
cs <= 1;
dout <= 0;
tx <= 0;
#1500 $finish;
end
/* GENERATE SCK WHEN outClock HIGH */
/* SCK = CLOCK/8 */
always @(clk) begin
if (outClock == 1) begin
sck = !sck;
#4;
end else
sck = 1;
end
/* SENT INIT ROUTINE */
always @(posedge init) begin
dout = 1;
/* FIRST DUMMY WORD */
cs = 0;
#4 outClock = 1;
#124 outClock = 0;
#4 cs = 1;
/* SECOND DUMMY WORD */
#16 cs = 0;
#4 outClock = 1;
#124 outClock = 0;
#4 cs = 1;
/* CONFIGURATION PARAMETERS */
#16 cs = 0;
#4 outClock = 1;
#76 dout = 0;
#8 dout = 1;
#42 outClock = 0;
#2 cs = 1;
#8 init = 0;
end
// CYCLE DATA AQUISITION AFTER INIT FINISHED
always @(negedge init) begin
#2 cs = 0;
#2 outClock = 1;
while (1) begin
wData[(16*wPointer)] = din;
/* test*/
bit =1 ;
repeat(15) begin
bit = bit + 1;
/* endtest */
// for (bit=1; bit>0; bit = bit + 1 ) begin
#4 wData[(16*wPointer)+bit] = din;
#4;
end
#8 wPointer = wPointer + 1;
cs = 1;
#4 cs = 0;
#4;
end
end
// MANCHESTER ENCODING
always @(posedge wPointer) begin
if (wData[3] || wData[2] || wData[1] || wData[0])
wData[0] = 0;
else
wData[1] = 1;
wData[1] = ^wData[15:4];
wData[2] = ^wData[15:10];
wData[3] = ^wData[9:4];
tx=0;
bit2=0;
repeat(16) begin
if (wData[bit2] == 1) begin
tx=1;
#4 tx=0;
#4;
end else begin
tx = 0;
#4 tx = 1;
#4;
end
bit2 = bit2 + 1;
end
tx=0;
end
always @(negedge wPointer) begin
if (wData[19] || wData[18] || wData[17] || wData[16])
wData[16] = 0;
else
wData[16] = 1;
wData[1] = ^wData[31:20];
wData[2] = ^wData[31:26];
wData[3] = ^wData[25:20];
tx=0;
bit2=0;
repeat(16) begin
if (wData[bit2+16] == 1) begin
tx=1;
#4 tx=0;
#4;
end else begin
tx = 0;
#4 tx = 1;
#4;
end
bit2 = bit2 + 1;
end
tx=0;
end
endmodule