help:assertions in verilog

[vittal]

Hi ,
I dont know what these assertions are .I have not used or came
across such things till now.
can any1 please explain them.
Thanks,
Vittal

 

[Rob Dekker]

"vittal" <vittal.patil@gmail.com> wrote in message news:1158726516.405139.58190@d34g2000cwd.googlegroups.com...

Hi ,
I dont know what these assertions are .I have not used or came
across such things till now.

If you don't know what they are, then you probably should not use them.
Assertions are complex and not easy to understand.
There are spectrum of books around explaining the basics.

can any1 please explain them.
Thanks,
Vittal

 

[Ajeetha]

Vittal,
Do google, you will find atleast half-a-dozen hits. Good ones to
get started are:

www.project-veripage.com
(I've contributed a PSL tutorial there, they also have SVA tutorial)

Our SVA Handbook is partly available via google books: see

http://books.google.co.in/books?vid=ISBN0970539479&id=m6CMyKhWX9YC&printsec=firstchapter&dq=sva+handbook&sig=ZxypLnBXLJuDSUNYRufIZY8NCJQ

http://books.google.co.in and search for "SVA Handbook"

www.synopsys.com/systemverilog has several papers. Mentor & CDN also
have techpapers on this.

What more do you need to get started?

Now a personal plug-in: my company, CVC is soon launching Assertion
training in Bangalore, write to ajeetha <> gmail.com for more.

HTH
Ajeetha, CVC
www.noveldv.com
www.abv-sva.org

vittal wrote:

Hi ,
I dont know what these assertions are .I have not used or came
across such things till now.
can any1 please explain them.
Thanks,
Vittal