Help: Altera megafunctions, Quartus II

[Bruce Varley]

I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used
the megafunction builder to create a FIFO memory, the .v file it generated
is similar to the virtual prototypes created for COM interfaces, with a data
structure and no functions. Is this all that the megafunction builder
provides, and I need to write my own Verilog code for eg. bumping the
address registers and generating handshake signals? Or is that code
generated for me already in a file that I haven't found yet? TIA

 

[KJ]

On Monday, April 14, 2014 9:17:25 AM UTC-4, Bruce Varley wrote:

I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the
megafunction builder to create a FIFO memory, the .v file it generated is
similar to the virtual prototypes created for COM interfaces, with a data
structure and no functions. Is this all that the megafunction builder provides,
and I need to write my own Verilog code for eg. bumping the address registers
and generating handshake signals? Or is that code generated for me already in a
file that I haven't found yet? TIA

Quartus has a megafunction for a FIFO, it is under 'Memory Compiler' that has a typical FIFO interface set of signals. Which megafunction part are you using?

Kevin Jennings

 

[Theo Markettos]

Bruce Varley <bv@nospam.com> wrote:

I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I
used the megafunction builder to create a FIFO memory, the .v file it
generated is similar to the virtual prototypes created for COM interfaces,
with a data structure and no functions. Is this all that the megafunction
builder provides, and I need to write my own Verilog code for eg. bumping
the address registers and generating handshake signals? Or is that code
generated for me already in a file that I haven't found yet? TIA

Megafunctions can instantiate internal FPGA structures - so the Megafunction
..v just instantiates another module without any actual code, which looks
like a prototype. The synthesis tool does however know about this and
'links' it with the right logic. The Megafunction header .v is mostly about
declaring the right parameters to the internal module, and also saving the
configuration (in comments at the bottom) so you can go in and edit it with
the GUI next time.

As well as physical hardware blocks, Megafunctions can instantiate private
Altera modules or encrypted IP, so you might not be able to see the
internals. You can also ask them to make testbenches to try out the
function in the simulator. I'd have a look at that first to see what the
interface looks like (the manual PDF will also tell you).

Theo

 

On Mon, 14 Apr 2014 06:43:38 -0700 (PDT), KJ
<kkjennings@sbcglobal.net> wrote:

On Monday, April 14, 2014 9:17:25 AM UTC-4, Bruce Varley wrote:
I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the
megafunction builder to create a FIFO memory, the .v file it generated is
similar to the virtual prototypes created for COM interfaces, with a data
structure and no functions. Is this all that the megafunction builder provides,
and I need to write my own Verilog code for eg. bumping the address registers
and generating handshake signals? Or is that code generated for me already in a
file that I haven't found yet? TIA

Quartus has a megafunction for a FIFO, it is under 'Memory Compiler' that has a typical FIFO interface set of signals. Which megafunction part are you using?

Kevin Jennings

DCFIFO, double clocked FIFO. Using the wizard was straightforward, but
after that I'm not sure whether I need to implement the glue logic,
such as the memory address incrementing and rollaround. Sounds like I
don't (once I work out what to do to make it happen).

Thanks for responses.