Help (again)

[David Wooff]

OK this time a different question - sorry this is a bit Noddy, but I'm just
starting to learn:
What is the purpose of the delay values (#10) added to verilog statements -
is this purely for simulation or does it have some impact on the actual
implementation in an FPGA?

--
Dave Wooff
dave@dmwooff.freeserve.co.uk

 

[Narendran Kumaraguru Nath]

David,
I've never worked on FPGA designs - hence I can't comment about it.
I use the #delay stmt's for
(1) Simulation - eg. when I wanted to create a clock signal.
(2) To delay the assignment to the last of the time period, using #0.
I don't think nowadays, people use these stmts to verify timing, instead they
define the timing arc and annotate an SDF file.
Thanks & Regards,
Naren.

"David Wooff" <dave@dmwooff.freeserve.co.uk> wrote in message news:<c18j89$r0h$1@news8.svr.pol.co.uk>...

OK this time a different question - sorry this is a bit Noddy, but I'm just
starting to learn:
What is the purpose of the delay values (#10) added to verilog statements -
is this purely for simulation or does it have some impact on the actual
implementation in an FPGA?

 

[David Wooff]

Thanks

--
Dave Wooff
dave@dmwooff.freeserve.co.uk
Narendran Kumaraguru Nathan <narenkumaraguru@yahoo.co.uk> wrote in message
news:f2914350.0402220915.3919d533@posting.google.com...

David,
I've never worked on FPGA designs - hence I can't comment about it.
I use the #delay stmt's for
(1) Simulation - eg. when I wanted to create a clock signal.
(2) To delay the assignment to the last of the time period, using #0.
I don't think nowadays, people use these stmts to verify timing, instead
they
define the timing arc and annotate an SDF file.
Thanks & Regards,
Naren.

"David Wooff" <dave@dmwooff.freeserve.co.uk> wrote in message
news:<c18j89$r0h$1@news8.svr.pol.co.uk>...
OK this time a different question - sorry this is a bit Noddy, but I'm
just
starting to learn:
What is the purpose of the delay values (#10) added to verilog
statements -
is this purely for simulation or does it have some impact on the actual
implementation in an FPGA?