Help... after hours of messing around my verilog still doesn

E

Equin

Guest
The below code is supposed to send a model-train from A to B to C. The train
goes from A to B and passes a fork. The fork is then switched and the train
reverses directions, after which it moves to point C where it stops.

There is a sensor at_c and at_b. To change directions, the train needs a
1-second pulse from my FPGA which is triggered with the trig signal that
goes to the seperate pulse module. The pulse is sent when at_b gives a high
signal. After this high signal the train will have passed the at_b sensor
and then pass it again, so the second time the at_b sensor is high the train
will not respond to an input from at_b. when the train reaches c at_c
becomes 1 and the train must stop.

The fork also needs a pulse to be switched.I know my fork module is alot
larger than necessary for this appliance but for something else I need it to
be this way.


Below is a finite state machine that should work, but it doesn't - when run
the train will move to C and stop when it reaches the b sensor. The FPGA
continuously sends the reverse-pulse and the fork is not switched. We've
been messing with this thing for ages and can't figure out what went wrong -
any help or tips would be greatly appreciated!



module train(clk,at_b,at_c,reset_,standstillrt_button,fork,
drive,trig);
//input at_a;
input at_b;
input at_c;
input reset_;
input clk;
input standstillrt_button;
output fork;reg fork;
output trig;reg trig;

output drive; reg drive;
reg [1:0] cs, ns;



parameter[2:0]
standstill = 0, move = 1, change_direction = 2, stop_=3, move2=4;

parameter[0:0]
dontchange_fork_direction = 0, change_fork_direction = 1;

parameter[0:0]
traindrive = 1, trainstop_it = 0;


always @ (posedge clk or posedge reset_)
if(reset_) cs = standstill;
else cs = ns;


always @ (cs or at_b or at_c or standstillrt_button)
case(cs)
standstill: begin

drive = trainstop_it;
trig = 0;
fork = dontchange_fork_direction;
if(standstillrt_button)
ns = move;
else
ns = standstill;
end
move: begin
drive = traindrive;
fork = dontchange_fork_direction;
trig = 0;
if(at_b)
ns = change_direction;
else if(at_c)
ns = stop_;
else
ns = move;
end

move2: begin
drive = traindrive;
fork = dontchange_fork_direction;
trig = 0;

if(at_c)
ns = stop_;
else
ns = move2;
end



change_direction: begin

// for(i=0;i<1000000000;i = i+1) begin
drive = traindrive;

fork = change_fork_direction;
ns = move2;
trig = 1;



end
/* gotoc: begin
direction = achteruit;
drive = traindrive;
fork = w_linksaf;
if(at_c)
ns = stop_;
else
ns = gotoc;
end*/



stop_: begin
drive = trainstop_it;
trig = 0;
fork = dontchange_fork_direction;
ns = stop_;
end
endcase

endmodule


module fork1_puls(clk, res, direction_in, fork_changer_straight,
fork_changer_turn);
input res, clk;

input direction_in;
parameter straight=0, turn=1;

output fork_changer_straight;
reg fork_changer_straight;
output fork_changer_turn;
reg fork_changer_turn;

reg last_direction;
reg[31:0] counter;
parameter[31:0] ticks_delay = 22000000; // is 1 sec.

always @ (posedge clk or posedge res)
begin
if (res)
begin
counter = ticks_delay;
last_direction = direction_in;
if (direction_in)
begin
fork_changer_straight = 1;
fork_changer_turn = 0;
end
else
begin
fork_changer_straight = 0;
fork_changer_turn = 1;
end
end
else if (last_direction!=direction_in)
begin
counter = ticks_delay;
last_direction = direction_in;
if (direction_in)
begin
fork_changer_straight = 1;
fork_changer_turn = 0;
end
else
begin
fork_changer_straight = 0;
fork_changer_turn = 1;
end
end
else if (counter>0) counter = counter - 1'b1;
else
begin
fork_changer_straight = 1;
fork_changer_turn = 1;
end
end

endmodule

module trainchange_direction_puls(trig, res, clk,
trainchange_direction_puls);
input trig;
input res;
input clk;
reg[31:0] counter;
output trainchange_direction_puls;
reg trainchange_direction_puls;

parameter[31:0] ticks_delay = 22000000; // is 1 sec.

always @ (posedge trig or posedge res or posedge clk)
begin
if (res)
begin
counter=0;
trainchange_direction_puls=0;
end
else if (trig)
begin
counter = ticks_delay;
trainchange_direction_puls=1;
end
else if (counter>0) counter = counter - 1'b1;
else trainchange_direction_puls=0;
end

endmodule
 
It looks like you're using blocking assignments in the sequential
portions of the design. In general, model combinatorial logic using
"always@*" blocks with blocking assignments and sequential logic using
"always@(posedge ...)" with non-blocking assignments. Check out the
following URL...

http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

David Walker

Equin wrote:
The below code is supposed to send a model-train from A to B to C. The train
goes from A to B and passes a fork. The fork is then switched and the train
reverses directions, after which it moves to point C where it stops.

There is a sensor at_c and at_b. To change directions, the train needs a
1-second pulse from my FPGA which is triggered with the trig signal that
goes to the seperate pulse module. The pulse is sent when at_b gives a high
signal. After this high signal the train will have passed the at_b sensor
and then pass it again, so the second time the at_b sensor is high the train
will not respond to an input from at_b. when the train reaches c at_c
becomes 1 and the train must stop.

The fork also needs a pulse to be switched.I know my fork module is alot
larger than necessary for this appliance but for something else I need it to
be this way.


Below is a finite state machine that should work, but it doesn't - when run
the train will move to C and stop when it reaches the b sensor. The FPGA
continuously sends the reverse-pulse and the fork is not switched. We've
been messing with this thing for ages and can't figure out what went wrong -
any help or tips would be greatly appreciated!



module train(clk,at_b,at_c,reset_,standstillrt_button,fork,
drive,trig);
//input at_a;
input at_b;
input at_c;
input reset_;
input clk;
input standstillrt_button;
output fork;reg fork;
output trig;reg trig;

output drive; reg drive;
reg [1:0] cs, ns;



parameter[2:0]
standstill = 0, move = 1, change_direction = 2, stop_=3, move2=4;

parameter[0:0]
dontchange_fork_direction = 0, change_fork_direction = 1;

parameter[0:0]
traindrive = 1, trainstop_it = 0;


always @ (posedge clk or posedge reset_)
if(reset_) cs = standstill;
else cs = ns;


always @ (cs or at_b or at_c or standstillrt_button)
case(cs)
standstill: begin

drive = trainstop_it;
trig = 0;
fork = dontchange_fork_direction;
if(standstillrt_button)
ns = move;
else
ns = standstill;
end
move: begin
drive = traindrive;
fork = dontchange_fork_direction;
trig = 0;
if(at_b)
ns = change_direction;
else if(at_c)
ns = stop_;
else
ns = move;
end

move2: begin
drive = traindrive;
fork = dontchange_fork_direction;
trig = 0;

if(at_c)
ns = stop_;
else
ns = move2;
end



change_direction: begin

// for(i=0;i<1000000000;i = i+1) begin
drive = traindrive;

fork = change_fork_direction;
ns = move2;
trig = 1;



end
/* gotoc: begin
direction = achteruit;
drive = traindrive;
fork = w_linksaf;
if(at_c)
ns = stop_;
else
ns = gotoc;
end*/



stop_: begin
drive = trainstop_it;
trig = 0;
fork = dontchange_fork_direction;
ns = stop_;
end
endcase

endmodule


module fork1_puls(clk, res, direction_in, fork_changer_straight,
fork_changer_turn);
input res, clk;

input direction_in;
parameter straight=0, turn=1;

output fork_changer_straight;
reg fork_changer_straight;
output fork_changer_turn;
reg fork_changer_turn;

reg last_direction;
reg[31:0] counter;
parameter[31:0] ticks_delay = 22000000; // is 1 sec.

always @ (posedge clk or posedge res)
begin
if (res)
begin
counter = ticks_delay;
last_direction = direction_in;
if (direction_in)
begin
fork_changer_straight = 1;
fork_changer_turn = 0;
end
else
begin
fork_changer_straight = 0;
fork_changer_turn = 1;
end
end
else if (last_direction!=direction_in)
begin
counter = ticks_delay;
last_direction = direction_in;
if (direction_in)
begin
fork_changer_straight = 1;
fork_changer_turn = 0;
end
else
begin
fork_changer_straight = 0;
fork_changer_turn = 1;
end
end
else if (counter>0) counter = counter - 1'b1;
else
begin
fork_changer_straight = 1;
fork_changer_turn = 1;
end
end

endmodule

module trainchange_direction_puls(trig, res, clk,
trainchange_direction_puls);
input trig;
input res;
input clk;
reg[31:0] counter;
output trainchange_direction_puls;
reg trainchange_direction_puls;

parameter[31:0] ticks_delay = 22000000; // is 1 sec.

always @ (posedge trig or posedge res or posedge clk)
begin
if (res)
begin
counter=0;
trainchange_direction_puls=0;
end
else if (trig)
begin
counter = ticks_delay;
trainchange_direction_puls=1;
end
else if (counter>0) counter = counter - 1'b1;
else trainchange_direction_puls=0;
end

endmodule
Click to expand...
 
is the train moving at all ?? i belive fork should give compilation
errors !!! as it is a reserved word in verilog

On Dec 6, 11:25 am, "dbwalker0...@gmail.com" <dbwalker0...@gmail.com>
wrote:
It looks like you're using blocking assignments in the sequential
portions of the design. In general, model combinatorial logic using
"always@*" blocks with blocking assignments and sequential logic using
"always@(posedge ...)" with non-blocking assignments. Check out the
following URL...

http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblockin...

David Walker

Equin wrote:
The below code is supposed to send a model-train from A to B to C. The train
goes from A to B and passes a fork. The fork is then switched and the train
reverses directions, after which it moves to point C where it stops.

There is a sensor at_c and at_b. To change directions, the train needs a
1-second pulse from my FPGA which is triggered with the trig signal that
goes to the seperate pulse module. The pulse is sent when at_b gives a high
signal. After this high signal the train will have passed the at_b sensor
and then pass it again, so the second time the at_b sensor is high the train
will not respond to an input from at_b. when the train reaches c at_c
becomes 1 and the train must stop.

The fork also needs a pulse to be switched.I know my fork module is alot
larger than necessary for this appliance but for something else I need it to
be this way.

Below is a finite state machine that should work, but it doesn't - when run
the train will move to C and stop when it reaches the b sensor. The FPGA
continuously sends the reverse-pulse and the fork is not switched. We've
been messing with this thing for ages and can't figure out what went wrong -
any help or tips would be greatly appreciated!

module train(clk,at_b,at_c,reset_,standstillrt_button,fork,
drive,trig);
//input at_a;
input at_b;
input at_c;
input reset_;
input clk;
input standstillrt_button;
output fork;reg fork;
output trig;reg trig;

output drive; reg drive;
reg [1:0] cs, ns;

parameter[2:0]
standstill = 0, move = 1, change_direction = 2, stop_=3, move2=4;

parameter[0:0]
dontchange_fork_direction = 0, change_fork_direction = 1;

parameter[0:0]
traindrive = 1, trainstop_it = 0;

always @ (posedge clk or posedge reset_)
if(reset_) cs = standstill;
else cs = ns;

always @ (cs or at_b or at_c or standstillrt_button)
case(cs)
standstill: begin

drive = trainstop_it;
trig = 0;
fork = dontchange_fork_direction;
if(standstillrt_button)
ns = move;
else
ns = standstill;
end
move: begin
drive = traindrive;
fork = dontchange_fork_direction;
trig = 0;
if(at_b)
ns = change_direction;
else if(at_c)
ns = stop_;
else
ns = move;
end

move2: begin
drive = traindrive;
fork = dontchange_fork_direction;
trig = 0;

if(at_c)
ns = stop_;
else
ns = move2;
end

change_direction: begin

// for(i=0;i<1000000000;i = i+1) begin
drive = traindrive;

fork = change_fork_direction;
ns = move2;
trig = 1;

end
/* gotoc: begin
direction = achteruit;
drive = traindrive;
fork = w_linksaf;
if(at_c)
ns = stop_;
else
ns = gotoc;
end*/

stop_: begin
drive = trainstop_it;
trig = 0;
fork = dontchange_fork_direction;
ns = stop_;
end
endcase

endmodule

module fork1_puls(clk, res, direction_in, fork_changer_straight,
fork_changer_turn);
input res, clk;

input direction_in;
parameter straight=0, turn=1;

output fork_changer_straight;
reg fork_changer_straight;
output fork_changer_turn;
reg fork_changer_turn;

reg last_direction;
reg[31:0] counter;
parameter[31:0] ticks_delay = 22000000; // is 1 sec.

always @ (posedge clk or posedge res)
begin
if (res)
begin
counter = ticks_delay;
last_direction = direction_in;
if (direction_in)
begin
fork_changer_straight = 1;
fork_changer_turn = 0;
end
else
begin
fork_changer_straight = 0;
fork_changer_turn = 1;
end
end
else if (last_direction!=direction_in)
begin
counter = ticks_delay;
last_direction = direction_in;
if (direction_in)
begin
fork_changer_straight = 1;
fork_changer_turn = 0;
end
else
begin
fork_changer_straight = 0;
fork_changer_turn = 1;
end
end
else if (counter>0) counter = counter - 1'b1;
else
begin
fork_changer_straight = 1;
fork_changer_turn = 1;
end
end

endmodule

module trainchange_direction_puls(trig, res, clk,
trainchange_direction_puls);
input trig;
input res;
input clk;
reg[31:0] counter;
output trainchange_direction_puls;
reg trainchange_direction_puls;

parameter[31:0] ticks_delay = 22000000; // is 1 sec.

always @ (posedge trig or posedge res or posedge clk)
begin
if (res)
begin
counter=0;
trainchange_direction_puls=0;
end
else if (trig)
begin
counter = ticks_delay;
trainchange_direction_puls=1;
end
else if (counter>0) counter = counter - 1'b1;
else trainchange_direction_puls=0;
end

endmodule
Click to expand...
 
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