Help: AC Analysis

I'm running ac analysis (from 1GHz to 5GHz) on a single NMOS but I'm
getting weird results. The schematic is setup as:

The drain is connected to a 2.2 V dc source for biasing and the gate is
connected to a 1.8V dc source for biasing also. Then, I just drive the
gate with ac magnitude = 1 V sin signal. I didn't want to do resistive
network for gate biasing because that's not the main issue. It's
sufficient for me to just place dc sources at the gate and drain. In
fact, biasing on a certain point is not important right now--it just
needs to be biased. Now, I run this circuit and I get very weird
results. For example, I was calculating input impedance at the gate
(Vi/Ii) and it came out too be way bigger than my hand calculations;
plus, the output signal didn't seem right among other things. I am
thinking something might be wrong with my dc/ac blocks. Please look at
my schematic and see if someone can spot a problem:
http://www.geocities.com/mxkdirs/acfet.html

I know I would need dc blocking caps to block dc signal but I'm not
sure if I need ac blocking inductors to block dc sources. And here
where my confusion is: if I block dc signal then my circuit might not
be biased because I'm running ac analysis from 1GHz to 5GHz. Thank
you.

Mike

 

Mike,

The setup appears to be correct. Yes, you need the
inductors to isolate the dc bias source for ac analysis.
One other option you could use in this case is Spectre's
analysis dependent switches. The switches allow you to
connect and disconnect elements based on the analysis
you are running. Could you provide some information on
the output signal you are seeing? Also are you calculating
the input impedance at dc or for the ac frequency range?
Shouldn't the dc impedance be pretty high? Are you using
hand calculated values for the calculation or are you using
the small signal parameters from the sumulator's dc operating
point calculation? In general, using the small signal parameters
from the dc operating points gives better correlation. There
are many second order effects that are difficult to include in
hand calculations.

Best Regards,

Brand Sheldon

mxkdirs@yahoo.com wrote:

I'm running ac analysis (from 1GHz to 5GHz) on a single NMOS but I'm
getting weird results. The schematic is setup as:

The drain is connected to a 2.2 V dc source for biasing and the gate is
connected to a 1.8V dc source for biasing also. Then, I just drive the
gate with ac magnitude = 1 V sin signal. I didn't want to do resistive
network for gate biasing because that's not the main issue. It's
sufficient for me to just place dc sources at the gate and drain. In
fact, biasing on a certain point is not important right now--it just
needs to be biased. Now, I run this circuit and I get very weird
results. For example, I was calculating input impedance at the gate
(Vi/Ii) and it came out too be way bigger than my hand calculations;
plus, the output signal didn't seem right among other things. I am
thinking something might be wrong with my dc/ac blocks. Please look at
my schematic and see if someone can spot a problem:
http://www.geocities.com/mxkdirs/acfet.html

I know I would need dc blocking caps to block dc signal but I'm not
sure if I need ac blocking inductors to block dc sources. And here
where my confusion is: if I block dc signal then my circuit might not
be biased because I'm running ac analysis from 1GHz to 5GHz. Thank
you.

Mike