help about operation :s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1

[VHDL_HELP]

Hi every body ,
i hope that you can help me , i want to do this operation:
s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
when i check the syntax , i have these errors
ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. * can
not have such operands in this context.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity operation is
Port ( clk : in STD_LOGIC;
c1 : in STD_LOGIC_VECTOR (7 downto 0);
c2 : in STD_LOGIC_VECTOR (7 downto 0);
c 3: in STD_LOGIC_VECTOR (7 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0);

end operation;

architecture Behavioral of operation is

begin

s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;

end Behavioral;

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and thanks for your help