HDL Synthesis to 2-input base function gate netlist

[Ralf Hildebrandt]

matthew.pullerits@gmail.com schrieb:

I need to obtain a decomposed (NAND/NOR; NAND/NOR/INV; or NAND/INV)
netlist from the synthesis of a given HDL (say, in VHDL). By
decomposed, I mean the gate netlist is to only contain two-input
functions.

I don't for what would this be good for, but what about building a
Synopsys library that contains only that cells you need? As an
alternative you can use a normal library and use the set_dont_use
attribute to all cells, you don't like.

Note, that synthesis tools often need more than a NAND to build
combinational logic. AFAIK in the synopsys manual is a not what kind of
cells are at least needed. And even the design analyzer should give you
a meaningful error.

Ralf

 

Hi all,

I need to obtain a decomposed (NAND/NOR; NAND/NOR/INV; or NAND/INV)
netlist from the synthesis of a given HDL (say, in VHDL). By
decomposed, I mean the gate netlist is to only contain two-input
functions.

I am quite new to using the Synopsys & SIS tools, and wonder if
someone might point me in the right direction to obtain this netlist
using these tools, or others which I might not be familiar with.

Any tips would be very much appreciated.

Thank you!
Matt