HDL Author, bus keyword and XST

G

Guillaume Zin

Guest
Hello,

I'm evaluating Mentor Graphics HDL Author 2005.2. I'm testing it with
the XST Xilinx synthesizer (from Xilinx 8.1 ISE webpack) but many tests
fail because HDL Author adds the "BUS" keyword to the inout ports when
converting schematics or FSM to VHDL. XST doesn't handle this keyword.

Is there an option in HDL Author to prevent the use of the "BUS" keyword ?

Thank you.

Guillaume.
 
Guillaume Zin wrote:

I'm evaluating Mentor Graphics HDL Author 2005.2. I'm testing it with
the XST Xilinx synthesizer (from Xilinx 8.1 ISE webpack) but many tests
fail because HDL Author adds the "BUS" keyword to the inout ports when
converting schematics or FSM to VHDL. XST doesn't handle this keyword.
Click to expand...
I prefer to write code my way
and to generate schematics and fsm graphics
from source using quartus or ise viewers.
I think HDL author/designer/etc has it backwards.

-- Mike Treseler
 
Mike Treseler a écrit :
I prefer to write code my way
and to generate schematics and fsm graphics
from source using quartus or ise viewers.
I think HDL author/designer/etc has it backwards.
Click to expand...
This is not my choice (I prefer VHDL or Verilog only designs), but I
must work on projects we got from another team. They used Mentor
Graphics tools and wrote VHDL sources but also used FSM and schematics.
I need the same tool to do modifications and I'm evaluating HDL Author
to see if is is enough for my purpose (there is HDL Designer too, which
is more expensive). But I'm a bit surprised of the lack of support for
XST because HDL Author gives the possibility to use it, but doesn't
produce VHDL code compatible. I think I'm missing something.

Guillaume.
 
Guillaume Zin wrote:

I need the same tool to do modifications and I'm evaluating HDL Author
to see if is is enough for my purpose (there is HDL Designer too, which
is more expensive).
Click to expand...
Maybe you can do this with just a text editor.

If the modification is an addition, supply
a new design entity, instance and port map.

If you must modify the base design, take ownership.
Check all of the code (generated or not)
into RCS or CVS or subversion and edit that.

But I'm a bit surprised of the lack of support for
XST because HDL Author gives the possibility to use it, but doesn't
produce VHDL code compatible. I think I'm missing something.
Click to expand...
Getting code generators to emit the desired code
is like pushing a rope. In many cases, the generated
code must be edited, and at that point, the
the graphical generator is out of the loop anyway.

-- Mike Treseler
 
Hi Guillaume,

This looks like a bug to me, I also use HDL designer for my designs and I
have never seen this behaviour. I would suggest you update your HDS to
2005.3 and speak to your support FAE. Does the supplied UART demo work?

Hans
www.ht-lab.com





"Guillaume Zin" <guillaume.zin@teleca.nospam.fr> wrote in message
news:e9lcod$9v9$1@s1.news.oleane.net...
Hello,

I'm evaluating Mentor Graphics HDL Author 2005.2. I'm testing it with the
XST Xilinx synthesizer (from Xilinx 8.1 ISE webpack) but many tests fail
because HDL Author adds the "BUS" keyword to the inout ports when
converting schematics or FSM to VHDL. XST doesn't handle this keyword.

Is there an option in HDL Author to prevent the use of the "BUS" keyword ?

Thank you.

Guillaume.
Click to expand...
 
Hi Mike,

Mike Treseler a écrit :
Maybe you can do this with just a text editor.

If the modification is an addition, supply
a new design entity, instance and port map.

If you must modify the base design, take ownership.
Check all of the code (generated or not)
into RCS or CVS or subversion and edit that.
Click to expand...
I agree, I may choose this solution if HDL Author is too expensive,
that's why I'm evaluating, I'm waiting for an offer from Mentor Graphics.

Guillaume.
 
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