HDL AUTHOR and SLL problem!

[a_Conan]

Hi,
I am using the HDL Author,
my problem that i have designed this code in HDL Author:
-----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY test3 IS
PORT(
In0 : IN unsigned (15 DOWNTO 0);
clock: IN std_logic;
Out0 : OUT unsigned (15 DOWNTO 0)
);


END test3 ;



ARCHITECTURE struct OF test3 IS

BEGIN
exdd: process(clock)
begin
Out0 <= In0 sll 2;
end process exdd;


END struct;


---------------------------

it gives this error message!!!!!!!!!!!!1

ERROR: D:/Sara/Tests/hdl/test3_struct.vhd(57): near "sll": expecting:
';'


Why Why !!!!

 

[Hans]

Works fine for me on HDS2005.3, perhaps the language is set for VHDL87?

Hans
www.ht-lab.com


"a_Conan" <hailconan@gmail.com> wrote in message
news:1147350702.146888.293420@v46g2000cwv.googlegroups.com...

Hi,
I am using the HDL Author,
my problem that i have designed this code in HDL Author:
-----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

ENTITY test3 IS
PORT(
In0 : IN unsigned (15 DOWNTO 0);
clock: IN std_logic;
Out0 : OUT unsigned (15 DOWNTO 0)
);


END test3 ;



ARCHITECTURE struct OF test3 IS

BEGIN
exdd: process(clock)
begin
Out0 <= In0 sll 2;
end process exdd;


END struct;


---------------------------

it gives this error message!!!!!!!!!!!!1

ERROR: D:/Sara/Tests/hdl/test3_struct.vhd(57): near "sll": expecting:
';'


Why Why !!!!

 

[a_Conan]

Hi, I have checked the
Options > VHDL > Style > VHDL Dialect (for checking)
and it is set to Any Dialect.
i tried with VHDL-93

but the same problem
by the way i use HDL Author 2002.1b (Build 7)

so what is the solution ?

 

[KJ]

According to "VHDL for Logic Synthesis Second Edition" by Andrew
Rushton, page 86....

"Shifting operators are only available in VHDL'93 and are only built in
for arrays of type boolean or bit. This means that the only standard
type thas has shift operators is bit_vector".

Not sure what the actual VHDL spec says about shift operators, but
that's Rushton's view of it.

KJ

 

[Mike Treseler]

a_Conan wrote:

I am using the HDL Author,
my problem that i have designed this code in HDL Author:
it gives this error message!!!!!!!!!!!!1
ERROR: D:/Sara/Tests/hdl/test3_struct.vhd(57):
near "sll": expecting:';'

I don't get any error with modelsim.
Try doing this.

use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

Note that numeric_std covers unsigned type all by itself.

Why Why !!!!

Sounds like your simulator does not support numeric_std.sll.
Try a different one.
Consider writing your own code on a good text editor.

-- Mike Treseler

 

[Hans]

Install 2005.3

I can't remember the 2002 version but you might want to check the options to
see if you can disable syntax checking...

Hans
www.ht-lab.com


"a_Conan" <hailconan@gmail.com> wrote in message
news:1147361167.927032.183420@g10g2000cwb.googlegroups.com...

Hi, I have checked the
Options > VHDL > Style > VHDL Dialect (for checking)
and it is set to Any Dialect.
i tried with VHDL-93

but the same problem
by the way i use HDL Author 2002.1b (Build 7)

so what is the solution ?