HDL Abstraction of Dynamic Logic

[Alex]

Hi Guys,

Maybe someone cope with similar problem and help.

I am creating a behavioral description of an asic, and I want it to be as
close as possible
to what would be on a chip in the end. As it all based on dynamic logic I
am a bit confused with
adequate description in VHDL.

Basically the question is how to describe the simple system which consist
of dynamic latch and a precharged bus.
As there are several registers connected to a bus it is necessary to keep
latch and a bus as separate instances.

If to decompose this problem even deeper it would sound - how to
describe a capacitor.

Sorry if the description is messy.
Thanks for help.

--
Alex

 

[Mike Treseler]

Alex wrote:

describe the simple system which
consist of dynamic latch and a precharged bus.

Dynamic logic uses a capacitor and precharge circuit as
a power supply. If you need to model these basic gates and
flops consider spice or vhdl-ams. Once these basic cells
are working, plain vhdl could be used for higher level
designs.

-- Mike Treseler

 

[Alex]

Thanks for your reply.

I was considering VHDL-AMS, but I have solved this problem with simple
usage
of st_logic_type (as the model is only for behvioral simulation).

So the basic idea of precharged bus is as follows - in case some one will
need it:


Port ( P : in std_logic; -- precharge
O : inout std_logic -- output
);

architecture
signal tmp_stor: std_logic;

begin
process(O,P)
begin
if O='0' then
if P='1' then O<='X';
else O<='L';
end if;
elsif P='1' then
O<='H';
end if;
ed process

In other words using week '0' and '1' simplify simulating such behaviour
as precharged logic.


Regards
--
Alex