HDB3 - clock recovery??

5

5hinka

Guest
Im designing Jitter Measurer for 2Mbit (HDB3) signal.
Input signal must be decoded from HDB3 to recover clock signal.
Is there any easy (or little bit hard) way to decode it (with error
correction)????

I was thinking about putting hdb3 signal into serial-in parallel-out shift
register
clocked with 11,12,13 * 2Mbit. Analizing Parallel out of this register will
enforce
11-13 multiply.
Maybe you know/see any easier solution??
Maybe sb seen anywhere in net some good publications about jitter
measurment??

Thx for help
Greetings from Poland
5hinka
 
On Tue, 18 Nov 2003 00:45:09 +0100, "5hinka" <anonim99@poczta.wp.pl>
wrote:
Im designing Jitter Measurer for 2Mbit (HDB3) signal.
Input signal must be decoded from HDB3 to recover clock signal.
Is there any easy (or little bit hard) way to decode it (with error
correction)????

I was thinking about putting hdb3 signal into serial-in parallel-out shift
register
clocked with 11,12,13 * 2Mbit. Analizing Parallel out of this register will
enforce
11-13 multiply.
Maybe you know/see any easier solution??
Maybe sb seen anywhere in net some good publications about jitter
measurment??
Low jitter clock recovery can be tricky.
We recently did a cascaded 2Mbps clock recovery system similar to HDB3
running through up to 12 series devices which recovered and
re-transmitted the clock in both directions. The final clock recovery
circuit used a tuned LC tank circuit on the front end of a 4046 PLL.
The DPLLs inside the FPGAs we had were useless for this task. Even the
4046 had to be a Phillips type, the other brands could not handle the
speed.
HDB3 in our system would have given too many problems in recovering an
extremely low jitter clock, given that it uses a non-deterministic run
length limited coding system. So we used an encoding scheme which
doubled the clock and encoded data to ensure that there was a
determinsitic clock signal every cycle. The energy of the clock signal
was thus confined to a narrow bandwidth which the PLL could extract a
very low jitter clock from, even after multiple regenerations. The
tank circuit was tuned to the clock frequency.

Don't have any web links to hand, sorry.

Regards
Dave :)
---------------------------
(remove the "_" from my email address to reply)
 
"5hinka" <anonim99@poczta.wp.pl> wrote in message
news:bpbmkp$231$1@nemesis.news.tpi.pl...
Im designing Jitter Measurer for 2Mbit (HDB3) signal.
Input signal must be decoded from HDB3 to recover clock signal.
Is there any easy (or little bit hard) way to decode it (with error
correction)????
Do what most Sane designers do - Go with an off the shelf solution to
extract the clocking from the E1:

PMC PM4351 (Comet)
PMC PM4314
PMC PM6341

I was thinking about putting hdb3 signal into serial-in parallel-out shift
register
clocked with 11,12,13 * 2Mbit. Analizing Parallel out of this register
will
enforce
11-13 multiply.
Maybe you know/see any easier solution??
Maybe sb seen anywhere in net some good publications about jitter
measurment??
Dual Trace Oscilliscope with Persistance (Tektronix TDS210/220 works well )
trigger one channel from a known good E1 (GPS clock etc) and connect the
other channel to the E1 being measured running infinite persistance and
thickness of the other trace after a few minutes gives a direct measurement
of jitter.

Usual commercial method is to generate a higher frequency signal from the
extracted clock, Measure the difference between the two clocks (the
reference and the measured clock) then calculate the change in the
difference between the two clocks (Jitter). The devices I have seen usually
have a ring of LEDs with a led being light to indicate the phase of the
measured signal wrt the reference E1.

thinking about it though try a full wave rectifier (many small signal diodes
ie IN914 should be fast enough ) feeding a schmitt trigger ( yes I have
glossed over input buffer details) thiswill give you a series of pulses from
HDB3 - at least one every 4 bits you could use this to clear a counter being
fed by a frequency which is a multiple of 2048000 Hz (32.768Mhz clock
modules are available and will provide 22.5 degree measurement which is
adequate for Practical applications) -this is a similair set up to
extracting timing from an Asynchronous data signal -
run the counter on your reference E1 then use the leading edge of the
measured E1 to latch the output of the counter and monitor the output from
this Latch - this will effectively tell you the difference in phase between
the two E1s and the variation in phase provides the jitter.

Regards
Richard Freeman
 

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